shijizhi.tan.rpt

十进制加法计数器.VHDL程序,可在Quratus 2中运行

; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; b[3] ; b[1] ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; b[0] ; b[3] ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; b[0] ; b[1] ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; b[1] ; d    ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; b[2] ; d    ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; b[2] ; b[3] ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; b[2] ; b[1] ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; b[2] ; b[2] ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; b[0] ; d    ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; b[0] ; b[0] ; clkin      ; clkin    ; None                        ; None                      ; None                    ;
+-------+------------------------------------------------+------+------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------+
; tco                                                          ;
+-------+--------------+------------+------+------+------------+
; Slack ; Required tco ; Actual tco ; From ; To   ; From Clock ;
+-------+--------------+------------+------+------+------------+
; N/A   ; None         ; 6.541 ns   ; b[1] ; a[1] ; clkin      ;
; N/A   ; None         ; 6.502 ns   ; b[0] ; a[0] ; clkin      ;
; N/A   ; None         ; 6.375 ns   ; d    ; c    ; clkin      ;
; N/A   ; None         ; 6.374 ns   ; b[2] ; a[2] ; clkin      ;
; N/A   ; None         ; 6.374 ns   ; b[3] ; a[3] ; clkin      ;
+-------+--------------+------------+------+------+------------+


+------------------------------------------------------------------------------+
; Minimum tco                                                                  ;
+---------------+------------------+----------------+------+------+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From ; To   ; From Clock ;
+---------------+------------------+----------------+------+------+------------+
; N/A           ; None             ; 6.374 ns       ; b[3] ; a[3] ; clkin      ;
; N/A           ; None             ; 6.374 ns       ; b[2] ; a[2] ; clkin      ;
; N/A           ; None             ; 6.375 ns       ; d    ; c    ; clkin      ;
; N/A           ; None             ; 6.502 ns       ; b[0] ; a[0] ; clkin      ;
; N/A           ; None             ; 6.541 ns       ; b[1] ; a[1] ; clkin      ;
+---------------+------------------+----------------+------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition
    Info: Processing started: Sat Aug 04 11:04:30 2007
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off shijizhi -c shijizhi --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node clkin is an undefined clock
Info: Clock clkin Internal fmax is restricted to 275.03 MHz between source register b[1] and destination register b[2]
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.178 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y13_N4; Fanout = 5; REG Node = 'b[1]'
            Info: 2: + IC(0.553 ns) + CELL(0.292 ns) = 0.845 ns; Loc. = LC_X2_Y13_N6; Fanout = 1; COMB Node = 'add~8'
            Info: 3: + IC(0.466 ns) + CELL(0.867 ns) = 2.178 ns; Loc. = LC_X2_Y13_N2; Fanout = 5; REG Node = 'b[2]'
            Info: Total cell delay = 1.159 ns ( 53.21 % )
            Info: Total interconnect delay = 1.019 ns ( 46.79 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock clkin to destination register is 2.745 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'clkin'
                Info: 2: + IC(0.565 ns) + CELL(0.711 ns) = 2.745 ns; Loc. = LC_X2_Y13_N2; Fanout = 5; REG Node = 'b[2]'
                Info: Total cell delay = 2.180 ns ( 79.42 % )
                Info: Total interconnect delay = 0.565 ns ( 20.58 % )
            Info: - Longest clock path from clock clkin to source register is 2.745 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'clkin'
                Info: 2: + IC(0.565 ns) + CELL(0.711 ns) = 2.745 ns; Loc. = LC_X2_Y13_N4; Fanout = 5; REG Node = 'b[1]'
                Info: Total cell delay = 2.180 ns ( 79.42 % )
                Info: Total interconnect delay = 0.565 ns ( 20.58 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock clkin to destination pin a[1] through register b[1] is 6.541 ns
    Info: + Longest clock path from clock clkin to source register is 2.745 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'clkin'
        Info: 2: + IC(0.565 ns) + CELL(0.711 ns) = 2.745 ns; Loc. = LC_X2_Y13_N4; Fanout = 5; REG Node = 'b[1]'
        Info: Total cell delay = 2.180 ns ( 79.42 % )
        Info: Total interconnect delay = 0.565 ns ( 20.58 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 3.572 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y13_N4; Fanout = 5; REG Node = 'b[1]'
        Info: 2: + IC(1.448 ns) + CELL(2.124 ns) = 3.572 ns; Loc. = PIN_1; Fanout = 0; PIN Node = 'a[1]'
        Info: Total cell delay = 2.124 ns ( 59.46 % )
        Info: Total interconnect delay = 1.448 ns ( 40.54 % )
Info: Minimum tco from clock clkin to destination pin a[3] through register b[3] is 6.374 ns
    Info: + Shortest clock path from clock clkin to source register is 2.745 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'clkin'
        Info: 2: + IC(0.565 ns) + CELL(0.711 ns) = 2.745 ns; Loc. = LC_X2_Y13_N9; Fanout = 4; REG Node = 'b[3]'
        Info: Total cell delay = 2.180 ns ( 79.42 % )
        Info: Total interconnect delay = 0.565 ns ( 20.58 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Shortest register to pin delay is 3.405 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y13_N9; Fanout = 4; REG Node = 'b[3]'
        Info: 2: + IC(1.297 ns) + CELL(2.108 ns) = 3.405 ns; Loc. = PIN_142; Fanout = 0; PIN Node = 'a[3]'
        Info: Total cell delay = 2.108 ns ( 61.91 % )
        Info: Total interconnect delay = 1.297 ns ( 38.09 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Aug 04 11:04:31 2007
    Info: Elapsed time: 00:00:00