tbxsp010.vhd

USB接口控制器参考设计VHDL代码,方便开发FPGA人员进行USB的开发

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-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--     
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--     
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--     
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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-- Project:      Full-Speed USB 1.1 Function Controller
-- File:         TBxsp010.vhd
-- Description:  Board-level testbench.
-- Version:      FB, 2000jun06
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.usbTSTPAK.all;
use work.TBxsp010pak.all;

entity TBxsp010 is
end TBxsp010;

--------------------------------------------------------------------------------
architecture Test of TBxsp010 is
	component XSP010
		port(
			-- usb phy
			vp:    in  STD_LOGIC;
			vm:    in  STD_LOGIC;
			vpo:   out STD_LOGIC;
			fse0:  out STD_LOGIC;
			oe:    out STD_LOGIC;
			-- 7-segment LEDs
			S0:    out STD_LOGIC;
			S1:    out STD_LOGIC;
			S2:    out STD_LOGIC;
			S3:    out STD_LOGIC;
			S4:    out STD_LOGIC;
			S5:    out STD_LOGIC;
			S6:    out STD_LOGIC
			);
	end component;
	
	--------------------
	-- UUT signals
	signal vp:        STD_LOGIC;
	signal vm:        STD_LOGIC;
	signal vpo:       STD_LOGIC;
	signal fse0:      STD_LOGIC;
	signal oe:        STD_LOGIC;
	
	--------------------
	-- test controller signals 
	signal clk48:     STD_LOGIC;
	signal rst:       STD_LOGIC;
	signal tb_xd:     STD_LOGIC;
	signal tb_x0:     STD_LOGIC;
	signal tb_clk:    STD_LOGIC;
	signal sim:       STD_LOGIC;
	signal stim:      STD_LOGIC;
	
	--------------------
	-- additional testbench signals
	signal urxd:      STD_LOGIC;
	signal urx0:      STD_LOGIC;
	signal utxd:      STD_LOGIC;
	signal utx0:      STD_LOGIC;
	signal utxoe:     STD_LOGIC;
	
begin
	
	--------------------
	-- Philips PDIUSBP11A
	vp   <= urxd      when urx0= '0' else '0';
	vm   <= not(urxd) when urx0= '0' else '0';
	utxd <= vpo;
	utx0 <= fse0;
	utxoe<= oe;
	
	--------------------
	Uctrl: usbTSTctrl port map(
		sim=> sim,
		stim=> stim,
		clk48=> clk48,
		rst=> rst,
		tb_xd=> tb_xd,
		tb_x0=> tb_x0,
		tb_clk=> tb_clk,
		uut_txd=> utxd,
		uut_tx0=> utx0,
		uut_rxd=> urxd,
		uut_rx0=> urx0
		);
	
	--------------------
	UUT: XSP010 port map(
		vp  => vp,
		vm  => vm,
		vpo => vpo,
		fse0=> fse0,
		oe  => oe);
	
	sim<= '1', '0' after 60us;
	
	--------------------
	process
	begin
		wait for 5us;
		
		--------------------
		GetDeviceDescriptor(tb_clk, tb_xd, tb_x0, stim);
		GetConfigDescriptor(tb_clk, tb_xd, tb_x0, stim);
		GetStringDescriptor(tb_clk, tb_xd, tb_x0, stim);
		SetAddress         (tb_clk, tb_xd, tb_x0, stim);
		SetConfiguration   (tb_clk, tb_xd, tb_x0, stim);
		GetStatus          (tb_clk, tb_xd, tb_x0, stim);
		GetReport          (tb_clk, tb_xd, tb_x0, stim);
		GetClassDescriptor (tb_clk, tb_xd, tb_x0, stim);
		InvalidRequest     (tb_clk, tb_xd, tb_x0, stim);
		
		--------------------
		stim<= '0';
		
		wait for 5us;
		
		assert FALSE
		report "successful end of simulation"
		severity FAILURE;
		
		wait;
	end process;
	
end Test;

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-- end of file