sram.vhd

USB接口控制器参考设计VHDL代码,方便开发FPGA人员进行USB的开发

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-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--     
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--     
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--     
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--------------------------------------------------------------------------------
-- Project:      Full-Speed USB 1.1 Function Controller
-- File:         SRAM.vhd
-- Description:  XSP-010 board, SRAM model with intel hex file load.
-- Version:      FB, 2000jul29
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_TEXTIO.all;	

library STD;
use STD.TEXTIO.all;

entity SRAM is
	generic (
		fname: STRING);                           -- path to intel hex file
	port(
		A:  in    STD_LOGIC_VECTOR(14 downto 0);  -- address bus
		D:  inout STD_LOGIC_VECTOR(7 downto 0);   -- data bus
		CE: in    STD_LOGIC;                      -- chip enable
		OE: in    STD_LOGIC;                      -- output enable
		WE: in    STD_LOGIC                       -- write enable
		);
end SRAM;

--------------------------------------------------------------------------------
architecture Sim of SRAM is
	type   Tmem  is array (0 to 4096) of STD_LOGIC_VECTOR (7 downto 0);
	signal mem: Tmem;
begin
	
	process(A, D, CE, OE, WE)
		
		procedure hexrecord(
			--------------------------------------------------------------------
			-- Intel hex records are contained in a file with one record per line. 
			-- Each line is in the following format: 
			--
			--     :<n_bytes> <address> 00 <data_byte 1> ... <data_byte n> <checksum> 
			--
			-- where: 
			--
			--     n_bytes   - the number of bytes defined by the record 
			--     address   - the address of the first byte 
			--     00        - zero
			--     data_byte - the contents of an individual byte. 
			--     checksum  - a value so that the sum of ALL the bytes 
			--                 (including the checksum) equals 0 modulo 256. 
			--
			-- The hex record is written as ASCII characters corresponding to the 
			-- hexadecimal values. For example, the hex records to encode the 
			-- sample data shown above are: 
			--
			--      :03012C0075812FAB
			--      :nnaaaa00ddddddcc
			--------------------------------------------------------------------
			constant fname: in  STRING;
			signal   mem:   out Tmem) is
			file     hexfile: TEXT open READ_MODE is fname;
			variable linebuf: LINE;
			variable char:    CHARACTER;
			variable nibble:  STD_LOGIC_VECTOR( 3 downto 0);
			variable count:   STD_LOGIC_VECTOR( 7 downto 0);
			variable addr:    STD_LOGIC_VECTOR(15 downto 0);
			variable byte:    STD_LOGIC_VECTOR( 7 downto 0);
			variable check:   STD_LOGIC_VECTOR( 7 downto 0);
		begin
			while not endfile(hexfile) loop
				readline(hexfile, linebuf);
				if linebuf'length> 8 then
					-- read ':'
					read(linebuf, char);
					-- read count
					hread(linebuf, nibble); count( 7 downto  4):= nibble;
					hread(linebuf, nibble); count( 3 downto  0):= nibble;
					-- read address
					hread(linebuf, nibble); addr(15 downto 12):= nibble;
					hread(linebuf, nibble); addr(11 downto  8):= nibble;
					hread(linebuf, nibble); addr( 7 downto  4):= nibble;
					hread(linebuf, nibble); addr( 3 downto  0):= nibble;
					-- skip 00
					hread(linebuf, nibble);
					hread(linebuf, nibble);
					-- read bytes
					for i in 1 to CONV_INTEGER(count) loop
						hread(linebuf, nibble); byte(7 downto 4):= nibble;
						hread(linebuf, nibble); byte(3 downto 0):= nibble;
						
						mem(CONV_INTEGER(addr))<= byte;
						
						addr:= addr + 1;
					end loop;
					-- read checksum
					hread(linebuf, nibble); check(7 downto 4):= nibble;
					hread(linebuf, nibble); check(3 downto 0):= nibble;
				end if;
			end loop;
		end procedure;
		
		variable initmem: BOOLEAN:= TRUE;
		
	begin
		
		if initmem then
			write( output, "SRAM initialization...." );
			hexrecord(fname, mem);
			initmem:= FALSE;
		else
			if CE= '0' then
				if WE= '0' then
					mem(CONV_INTEGER(A))<= D;
					-- assert FALSE
					-- report "write access to SRAM!"
					-- severity FAILURE;
				end if;
				
				if OE= '0' then
					D<= mem(CONV_INTEGER(A));
				else 
					D<= (others=> 'Z');
				end if;
			end if;
		end if;
	end process;
	
end Sim;

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-- end of file