phase.vhd

实现两路数字信号的鉴相功能

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entitY phase is
   port( clk_32M:in std_logic;
         X0,X1:  in std_logic;
         O0,O1,O2,O3: out std_logic_vector(6 downto 0));    						  
end phase;


architecture behav of phase is
          
    
  signal Z0,Z1,en1,ld,clear: std_logic:='0';
  signal cnt: std_logic_vector(15 downto 0):= (others => '0');
  signal cnt0: std_logic_vector(3 downto 0):= (others => '0');
  signal cnt1: std_logic_vector(3 downto 0):= (others => '0');
  signal cnt2: std_logic_vector(7 downto 0):= (others => '0');
  signal cnt_value0,cnt_value1,cnt_value2,cnt_value3:std_logic_vector(3 downto 0):= (others => '0');
  signal latched_value1,latched_value2,latched_value3,latched_value4:std_logic_vector(3 downto 0):= (others => '0');

begin
   Z0<= x0 xor x1;
   Z1<= Z0 and X0;
   
   
   process(clk_32M)
       begin
           if(clk_32M'event and clk_32M='1') then
               
                 if cnt="1111111111111111" then --36000
                    en1<='1';  
                    cnt<="0000000000000000";
                    else cnt<=cnt+1;
                 end if;
                  if cnt="1000110010011111" then
                    en1<='0';
                    ld<='1';   --????
                  else ld<='0';
                  end if;
                  
                  if cnt="1000110011111111" then
                    clear<='1';  --????
                  else clear<='0';
                  end if;
                  
              
              
                 if(ld='1') then  --??
                 
                latched_value1<=cnt_value0;
                latched_value2<=cnt_value1;
                latched_value3<=cnt_value2;
                latched_value4<=cnt_value3; 
                end if;
        --        en2<=en1;
        
              if(clear='1') then  --??
                  cnt_value0<="0000";
                 cnt_value1<="0000";
                 cnt_value2<="0000";
                 cnt_value3<="0000";  
               end if;
              
               if(cnt0="1001") then
                 cnt0<="0000";
               if(en1='1' and Z1='1') then
                 if(cnt_value0="1001")then  --0.1?
                   cnt_value0<="0000";
                  if(cnt_value1="1001")then --1?
                    cnt_value1<="0000";
                     if(cnt_value2="1001")then  --10?
                        cnt_value2<="0000";
                        if(cnt_value3="1001")then  --100?
                            cnt_value3<="0000";
                            
                            else cnt_value3<=cnt_value3+'1';
                        end if;
                       else cnt_value2<=cnt_value2+'1';
                   end if;
                   else cnt_value1<=cnt_value1+'1'; 
               end if;
               else cnt_value0<=cnt_value0+'1';
             end if;
            end if;
           else 
               cnt0<=cnt0+'1';
        end if; 
      end if;
   end process;
   
   
   

   process(latched_value1,latched_value2,latched_value3,latched_value4)
       begin      --????
                      
            case latched_value1 is
		          when "0000" => O0 <= "0000001";
		          when "0001" => O0 <= "1001111";
			       when "0010" => O0 <= "0010010";
		          when "0011" => O0 <= "0000110";
		          when "0100" => O0 <= "1001100";
		          when "0101" => O0 <= "0100100";
		          when "0110" => O0 <= "0100000";
		          when "0111" => O0 <= "0001111";
		          when "1000" => O0 <= "0000000";
		          when "1001" => O0 <= "0000100";
		          when others => O0 <= "-------";
                end case;
		      case latched_value2 is
		          when "0000" => O1 <= "0000001";
		          when "0001" => O1 <= "1001111";
		 	     when "0010" => O1 <= "0010010";
			     when "0011" => O1 <= "0000110";
			     when "0100" => O1 <= "1001100";
			     when "0101" => O1 <= "0100100";
			     when "0110" => O1 <= "0100000";
			     when "0111" => O1 <= "0001111";
			     when "1000" => O1 <= "0000000";
			     when "1001" => O1 <= "0000100";
			     when others => O1 <= "-------";
                end case;
			 case latched_value3 is
		          when "0000" => O2 <= "0000001";
			     when "0001" => O2 <= "1001111";
			     when "0010" => O2 <= "0010010";
			     when "0011" => O2 <= "0000110";
			     when "0100" => O2 <= "1001100";
			     when "0101" => O2 <= "0100100";
			     when "0110" => O2 <= "0100000";
			     when "0111" => O2 <= "0001111";
			     when "1000" => O2 <= "0000000";
			     when "1001" => O2 <= "0000100";
			     when others => O2 <= "-------";
                end case;
		      case latched_value4 is
			     when "0000" => O3 <= "0000001";
			     when "0001" => O3 <= "1001111";
			     when "0010" => O3 <= "0010010";
			     when "0011" => O3 <= "0000110";
			     when "0100" => O3 <= "1001100";
			     when "0101" => O3 <= "0100100";
		        when "0110" => O3 <= "0100000";
			     when "0111" => O3 <= "0001111";
			     when "1000" => O3 <= "0000000";
			     when "1001" => O3 <= "0000100";
			     when others => O3 <= "-------";
                end case;
                
                
    end process;

  
            
  end behav;