📄 cpld_for_lcd.tan.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" { } { } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 29 16:51:25 2007 " "Info: Processing started: Tue May 29 16:51:25 2007" { } { } 0} } { } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off cpld_for_lcd -c cpld_for_lcd " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cpld_for_lcd -c cpld_for_lcd" { } { } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "DE\$latch~10 " "Info: Node \"DE\$latch~10\"" { } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 15 -1 0 } } } 0} } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 15 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "HS\$latch~10 " "Info: Node \"HS\$latch~10\"" { } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 15 -1 0 } } } 0} } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 15 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "VS\$latch~10 " "Info: Node \"VS\$latch~10\"" { } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 15 -1 0 } } } 0} } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 15 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "BLUE\[7\]\$latch~10 " "Info: Node \"BLUE\[7\]\$latch~10\"" { } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0} } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "BLUE\[6\]\$latch~10 " "Info: Node \"BLUE\[6\]\$latch~10\"" { } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0} } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "BLUE\[5\]\$latch~10 " "Info: Node \"BLUE\[5\]\$latch~10\"" { } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0} } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "BLUE\[4\]\$latch~10 " "Info: Node \"BLUE\[4\]\$latch~10\"" { } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0} } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "BLUE\[3\]\$latch~10 " "Info: Node \"BLUE\[3\]\$latch~10\"" { } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0} } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "GREEN\[7\]\$latch~10 " "Info: Node \"GREEN\[7\]\$latch~10\"" { } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0} } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "GREEN\[6\]\$latch~10 " "Info: Node \"GREEN\[6\]\$latch~10\"" { } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0} } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "GREEN\[5\]\$latch~10 " "Info: Node \"GREEN\[5\]\$latch~10\"" { } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0} } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "GREEN\[4\]\$latch~10 " "Info: Node \"GREEN\[4\]\$latch~10\"" { } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0} } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "GREEN\[3\]\$latch~10 " "Info: Node \"GREEN\[3\]\$latch~10\"" { } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0} } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "RED\[7\]\$latch~10 " "Info: Node \"RED\[7\]\$latch~10\"" { } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0} } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "RED\[6\]\$latch~10 " "Info: Node \"RED\[6\]\$latch~10\"" { } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0} } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "RED\[5\]\$latch~10 " "Info: Node \"RED\[5\]\$latch~10\"" { } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0} } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "RED\[4\]\$latch~10 " "Info: Node \"RED\[4\]\$latch~10\"" { } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0} } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "RED\[3\]\$latch~10 " "Info: Node \"RED\[3\]\$latch~10\"" { } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0} } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "RED\[0\]\$latch~26 " "Info: Node \"RED\[0\]\$latch~26\"" { } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0} } { { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "MSTR_nRST BLUE\[2\] 17.700 ns Longest " "Info: Longest tpd from source pin \"MSTR_nRST\" to destination pin \"BLUE\[2\]\" is 17.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns MSTR_nRST 1 PIN PIN_89 57 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_89; Fanout = 57; PIN Node = 'MSTR_nRST'" { } { { "E:/test/verilog_hdl/24bit_display/db/cpld_for_lcd_cmp.qrpt" "" { Report "E:/test/verilog_hdl/24bit_display/db/cpld_for_lcd_cmp.qrpt" Compiler "cpld_for_lcd" "UNKNOWN" "V1" "E:/test/verilog_hdl/24bit_display/db/cpld_for_lcd.quartus_db" { Floorplan "E:/test/verilog_hdl/24bit_display/" "" "" { MSTR_nRST } "NODE_NAME" } "" } } { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 12 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.300 ns) 8.800 ns RED\[0\]\$latch~26 2 COMB LOOP LC33 11 " "Info: 2: + IC(0.000 ns) + CELL(6.300 ns) = 8.800 ns; Loc. = LC33; Fanout = 11; COMB LOOP Node = 'RED\[0\]\$latch~26'" { { "Info" "ITDB_PART_OF_SCC" "RED\[0\]\$latch~26 LC33 " "Info: Loc. = LC33; Node \"RED\[0\]\$latch~26\"" { } { { "E:/test/verilog_hdl/24bit_display/db/cpld_for_lcd_cmp.qrpt" "" { Report "E:/test/verilog_hdl/24bit_display/db/cpld_for_lcd_cmp.qrpt" Compiler "cpld_for_lcd" "UNKNOWN" "V1" "E:/test/verilog_hdl/24bit_display/db/cpld_for_lcd.quartus_db" { Floorplan "E:/test/verilog_hdl/24bit_display/" "" "" { RED[0]$latch~26 } "NODE_NAME" } "" } } } 0} } { { "E:/test/verilog_hdl/24bit_display/db/cpld_for_lcd_cmp.qrpt" "" { Report "E:/test/verilog_hdl/24bit_display/db/cpld_for_lcd_cmp.qrpt" Compiler "cpld_for_lcd" "UNKNOWN" "V1" "E:/test/verilog_hdl/24bit_display/db/cpld_for_lcd.quartus_db" { Floorplan "E:/test/verilog_hdl/24bit_display/" "" "" { RED[0]$latch~26 } "NODE_NAME" } "" } } { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } { "E:/test/verilog_hdl/24bit_display/db/cpld_for_lcd_cmp.qrpt" "" { Report "E:/test/verilog_hdl/24bit_display/db/cpld_for_lcd_cmp.qrpt" Compiler "cpld_for_lcd" "UNKNOWN" "V1" "E:/test/verilog_hdl/24bit_display/db/cpld_for_lcd.quartus_db" { Floorplan "E:/test/verilog_hdl/24bit_display/" "" "6.300 ns" { MSTR_nRST RED[0]$latch~26 } "NODE_NAME" } "" } } { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(4.400 ns) 16.100 ns RED\[0\]\$latch~28 3 COMB LC102 1 " "Info: 3: + IC(2.900 ns) + CELL(4.400 ns) = 16.100 ns; Loc. = LC102; Fanout = 1; COMB Node = 'RED\[0\]\$latch~28'" { } { { "E:/test/verilog_hdl/24bit_display/db/cpld_for_lcd_cmp.qrpt" "" { Report "E:/test/verilog_hdl/24bit_display/db/cpld_for_lcd_cmp.qrpt" Compiler "cpld_for_lcd" "UNKNOWN" "V1" "E:/test/verilog_hdl/24bit_display/db/cpld_for_lcd.quartus_db" { Floorplan "E:/test/verilog_hdl/24bit_display/" "" "7.300 ns" { RED[0]$latch~26 RED[0]$latch~28 } "NODE_NAME" } "" } } { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 17.700 ns BLUE\[2\] 4 PIN PIN_67 0 " "Info: 4: + IC(0.000 ns) + CELL(1.600 ns) = 17.700 ns; Loc. = PIN_67; Fanout = 0; PIN Node = 'BLUE\[2\]'" { } { { "E:/test/verilog_hdl/24bit_display/db/cpld_for_lcd_cmp.qrpt" "" { Report "E:/test/verilog_hdl/24bit_display/db/cpld_for_lcd_cmp.qrpt" Compiler "cpld_for_lcd" "UNKNOWN" "V1" "E:/test/verilog_hdl/24bit_display/db/cpld_for_lcd.quartus_db" { Floorplan "E:/test/verilog_hdl/24bit_display/" "" "1.600 ns" { RED[0]$latch~28 BLUE[2] } "NODE_NAME" } "" } } { "cpld_for_lcd.v" "" { Text "E:/test/verilog_hdl/24bit_display/cpld_for_lcd.v" 16 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.800 ns 83.62 % " "Info: Total cell delay = 14.800 ns ( 83.62 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.900 ns 16.38 % " "Info: Total interconnect delay = 2.900 ns ( 16.38 % )" { } { } 0} } { { "E:/test/verilog_hdl/24bit_display/db/cpld_for_lcd_cmp.qrpt" "" { Report "E:/test/verilog_hdl/24bit_display/db/cpld_for_lcd_cmp.qrpt" Compiler "cpld_for_lcd" "UNKNOWN" "V1" "E:/test/verilog_hdl/24bit_display/db/cpld_for_lcd.quartus_db" { Floorplan "E:/test/verilog_hdl/24bit_display/" "" "17.700 ns" { MSTR_nRST RED[0]$latch~26 RED[0]$latch~28 BLUE[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "17.700 ns" { MSTR_nRST MSTR_nRST~out RED[0]$latch~26 RED[0]$latch~28 BLUE[2] } { 0.000ns 0.000ns 0.000ns 2.900ns 0.000ns } { 0.000ns 2.500ns 6.300ns 4.400ns 1.600ns } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue May 29 16:51:26 2007 " "Info: Processing ended: Tue May 29 16:51:26 2007" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0} } { } 0}
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