📄 cpld_for_lcd.fit.rpt
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; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ;
; 2.5 V ; 10 pF ; Not Available ;
+--------------+-------+------------------------+
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+----------------------------------------------------------------------+
; Fitter Resource Utilization by Entity ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |cpld_for_lcd ; 27 ; 64 ; |cpld_for_lcd ;
+----------------------------+------------+------+---------------------+
+---------------------------------+
; Non-Global High Fan-Out Signals ;
+-------------------+-------------+
; Name ; Fan-Out ;
+-------------------+-------------+
; MSTR_nRST ; 19 ;
; RED[0]$latch~26 ; 10 ;
; DE$latch~10 ; 2 ;
; HS$latch~10 ; 2 ;
; VS$latch~10 ; 2 ;
; BLUE[7]$latch~10 ; 2 ;
; BLUE[6]$latch~10 ; 2 ;
; BLUE[5]$latch~10 ; 2 ;
; BLUE[4]$latch~10 ; 2 ;
; BLUE[3]$latch~10 ; 2 ;
; GREEN[7]$latch~10 ; 2 ;
; GREEN[6]$latch~10 ; 2 ;
; GREEN[5]$latch~10 ; 2 ;
; GREEN[4]$latch~10 ; 2 ;
; GREEN[3]$latch~10 ; 2 ;
; RED[7]$latch~10 ; 2 ;
; RED[6]$latch~10 ; 2 ;
; RED[5]$latch~10 ; 2 ;
; RED[4]$latch~10 ; 2 ;
; RED[3]$latch~10 ; 2 ;
; LCD_D[15] ; 1 ;
; LCD_D[14] ; 1 ;
; LCD_D[13] ; 1 ;
; LCD_D[12] ; 1 ;
; LCD_D[11] ; 1 ;
; LCD_D[10] ; 1 ;
; LCD_D[9] ; 1 ;
; LCD_D[8] ; 1 ;
; LCD_D[7] ; 1 ;
; LCD_D[6] ; 1 ;
; LCD_D[5] ; 1 ;
; LCD_D[4] ; 1 ;
; LCD_D[3] ; 1 ;
; LCD_D[2] ; 1 ;
; LCD_D[1] ; 1 ;
; LCD_D[0] ; 1 ;
; LCD_VSYNC ; 1 ;
; LCD_HSYNC ; 1 ;
; LCD_MDISP ; 1 ;
; RED[0]$latch~42 ; 1 ;
; RED[0]$latch~40 ; 1 ;
; RED[0]$latch~38 ; 1 ;
; RED[0]$latch~36 ; 1 ;
; RED[0]$latch~34 ; 1 ;
; RED[0]$latch~32 ; 1 ;
; RED[0]$latch~30 ; 1 ;
; RED[0]$latch~28 ; 1 ;
+-------------------+-------------+
+------------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+-------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+-------------------+
; Output enables ; 0 / 6 ( 0 % ) ;
; PIA buffers ; 44 / 288 ( 15 % ) ;
; PIAs ; 46 / 288 ( 15 % ) ;
+----------------------------+-------------------+
+----------------------------------------------------------------------------+
; LAB External Interconnect ;
+----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 5.75) ; Number of LABs (Total = 5) ;
+----------------------------------------------+-----------------------------+
; 0 ; 3 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 1 ;
; 10 ; 1 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 1 ;
+----------------------------------------------+-----------------------------+
+----------------------------------------------------------------------+
; LAB Macrocells ;
+----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 3.38) ; Number of LABs (Total = 5) ;
+----------------------------------------+-----------------------------+
; 0 ; 3 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 1 ;
; 8 ; 1 ;
+----------------------------------------+-----------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC14 ; LCD_D[14], MSTR_nRST, BLUE[7]$latch~10 ; BLUE[7]$latch~10, BLUE[7] ;
; A ; LC13 ; LCD_D[13], MSTR_nRST, BLUE[6]$latch~10 ; BLUE[6]$latch~10, BLUE[6] ;
; A ; LC16 ; RED[0]$latch~26 ; BLUE[1] ;
; A ; LC11 ; RED[0]$latch~26 ; BLUE[0] ;
; A ; LC6 ; LCD_D[5], MSTR_nRST, GREEN[3]$latch~10 ; GREEN[3]$latch~10, GREEN[3] ;
; A ; LC8 ; LCD_D[6], MSTR_nRST, GREEN[4]$latch~10 ; GREEN[4]$latch~10, GREEN[4] ;
; A ; LC9 ; LCD_D[7], MSTR_nRST, GREEN[5]$latch~10 ; GREEN[5]$latch~10, GREEN[5] ;
; A ; LC5 ; LCD_D[9], MSTR_nRST, GREEN[7]$latch~10 ; GREEN[7]$latch~10, GREEN[7] ;
; B ; LC17 ; LCD_VSYNC, MSTR_nRST, VS$latch~10 ; VS$latch~10, VS ;
; B ; LC25 ; RED[0]$latch~26 ; GREEN[2] ;
; B ; LC29 ; LCD_D[8], MSTR_nRST, GREEN[6]$latch~10 ; GREEN[6]$latch~10, GREEN[6] ;
; B ; LC19 ; LCD_D[4], MSTR_nRST, RED[7]$latch~10 ; RED[7]$latch~10, RED[7] ;
; B ; LC24 ; RED[0]$latch~26 ; GREEN[1] ;
; B ; LC21 ; LCD_D[2], MSTR_nRST, RED[5]$latch~10 ; RED[5]$latch~10, RED[5] ;
; B ; LC22 ; RED[0]$latch~26 ; GREEN[0] ;
; C ; LC40 ; RED[0]$latch~26 ; RED[2] ;
; C ; LC37 ; RED[0]$latch~26 ; RED[1] ;
; C ; LC46 ; LCD_HSYNC, MSTR_nRST, HS$latch~10 ; HS$latch~10, HS ;
; C ; LC43 ; LCD_D[1], MSTR_nRST, RED[4]$latch~10 ; RED[4]$latch~10, RED[4] ;
; C ; LC41 ; LCD_D[0], MSTR_nRST, RED[3]$latch~10 ; RED[3]$latch~10, RED[3] ;
; C ; LC33 ; LCD_D[15], MSTR_nRST, RED[0]$latch~26 ; RED[0]$latch~26, RED[0], RED[0]$latch~28, RED[0]$latch~30, RED[0]$latch~32, RED[0]$latch~34, RED[0]$latch~36, RED[0]$latch~38, RED[0]$latch~40, RED[0]$latch~42 ;
; D ; LC59 ; LCD_MDISP, MSTR_nRST, DE$latch~10 ; DE$latch~10, DE ;
; D ; LC61 ; LCD_D[3], MSTR_nRST, RED[6]$latch~10 ; RED[6]$latch~10, RED[6] ;
; G ; LC102 ; RED[0]$latch~26 ; BLUE[2] ;
; G ; LC109 ; LCD_D[12], MSTR_nRST, BLUE[5]$latch~10 ; BLUE[5]$latch~10, BLUE[5] ;
; G ; LC105 ; LCD_D[11], MSTR_nRST, BLUE[4]$latch~10 ; BLUE[4]$latch~10, BLUE[4] ;
; G ; LC104 ; LCD_D[10], MSTR_nRST, BLUE[3]$latch~10 ; BLUE[3]$latch~10, BLUE[3] ;
+-----+------------+----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Tue May 29 16:51:20 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off cpld_for_lcd -c cpld_for_lcd
Info: Selected device EPM3128ATC100-10 for design "cpld_for_lcd"
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Tue May 29 16:51:21 2007
Info: Elapsed time: 00:00:01
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