cpld_for_lcd.map.rpt

一个VEILOG HDL程序

; Maximum fan-out      ; 19                   ;
; Total fan-out        ; 92                   ;
; Average fan-out      ; 1.06                 ;
+----------------------+----------------------+


+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                  ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |cpld_for_lcd              ; 27         ; 60   ; |cpld_for_lcd       ;
+----------------------------+------------+------+---------------------+


+----------------------------------------------------+
; User-Specified and Inferred Latches                ;
+-----------------------------------------------+----+
; Latch Name                                    ;    ;
+-----------------------------------------------+----+
; RED[0]$latch                                  ;    ;
; RED[1]$latch                                  ;    ;
; RED[2]$latch                                  ;    ;
; RED[3]$latch                                  ;    ;
; RED[4]$latch                                  ;    ;
; RED[5]$latch                                  ;    ;
; RED[6]$latch                                  ;    ;
; RED[7]$latch                                  ;    ;
; GREEN[0]$latch                                ;    ;
; GREEN[1]$latch                                ;    ;
; GREEN[2]$latch                                ;    ;
; GREEN[3]$latch                                ;    ;
; GREEN[4]$latch                                ;    ;
; GREEN[5]$latch                                ;    ;
; GREEN[6]$latch                                ;    ;
; GREEN[7]$latch                                ;    ;
; BLUE[0]$latch                                 ;    ;
; BLUE[1]$latch                                 ;    ;
; BLUE[2]$latch                                 ;    ;
; BLUE[3]$latch                                 ;    ;
; BLUE[4]$latch                                 ;    ;
; BLUE[5]$latch                                 ;    ;
; BLUE[6]$latch                                 ;    ;
; BLUE[7]$latch                                 ;    ;
; VS$latch                                      ;    ;
; HS$latch                                      ;    ;
; DE$latch                                      ;    ;
; Number of user-specified and inferred latches ; 27 ;
+-----------------------------------------------+----+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/test/verilog_hdl/24bit_display/cpld_for_lcd.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Tue May 29 16:51:17 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cpld_for_lcd -c cpld_for_lcd
Info: Found 1 design units, including 1 entities, in source file cpld_for_lcd.v
    Info: Found entity 1: cpld_for_lcd
Info: Elaborating entity "cpld_for_lcd" for the top level hierarchy
Warning: Verilog HDL Always Construct warning at cpld_for_lcd.v(58): variable "VS_BUF" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL Always Construct warning at cpld_for_lcd.v(59): variable "HS_BUF" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL Always Construct warning at cpld_for_lcd.v(60): variable "DE_BUF" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL Always Construct warning at cpld_for_lcd.v(48): variable "VS" may not be assigned a new value in every possible path through the Always Construct.  Variable "VS" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at cpld_for_lcd.v(48): variable "HS" may not be assigned a new value in every possible path through the Always Construct.  Variable "HS" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at cpld_for_lcd.v(48): variable "DE" may not be assigned a new value in every possible path through the Always Construct.  Variable "DE" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at cpld_for_lcd.v(48): variable "BLUE" may not be assigned a new value in every possible path through the Always Construct.  Variable "BLUE" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at cpld_for_lcd.v(48): variable "GREEN" may not be assigned a new value in every possible path through the Always Construct.  Variable "GREEN" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at cpld_for_lcd.v(48): variable "RED" may not be assigned a new value in every possible path through the Always Construct.  Variable "RED" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Ignored 19 buffer(s)
    Info: Ignored 19 SOFT buffer(s)
Info: Duplicate LATCH primitives merged into single LATCH primitive
    Info: Duplicate LATCH primitive "BLUE[2]$latch" merged with LATCH primitive "RED[0]$latch"
    Info: Duplicate LATCH primitive "BLUE[1]$latch" merged with LATCH primitive "RED[0]$latch"
    Info: Duplicate LATCH primitive "BLUE[0]$latch" merged with LATCH primitive "RED[0]$latch"
    Info: Duplicate LATCH primitive "GREEN[2]$latch" merged with LATCH primitive "RED[0]$latch"
    Info: Duplicate LATCH primitive "GREEN[1]$latch" merged with LATCH primitive "RED[0]$latch"
    Info: Duplicate LATCH primitive "GREEN[0]$latch" merged with LATCH primitive "RED[0]$latch"
    Info: Duplicate LATCH primitive "RED[2]$latch" merged with LATCH primitive "RED[0]$latch"
    Info: Duplicate LATCH primitive "RED[1]$latch" merged with LATCH primitive "RED[0]$latch"
Warning: Design contains 13 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "BUFFERED_CLOCK"
    Warning: No output dependent on input pin "LCD_TYPE[0]"
    Warning: No output dependent on input pin "LCD_TYPE[1]"
    Warning: No output dependent on input pin "LCD_TYPE[2]"
    Warning: No output dependent on input pin "LCD_DON"
    Warning: No output dependent on input pin "LCD_REV"
    Warning: No output dependent on input pin "LCD_CLS"
    Warning: No output dependent on input pin "LCD_PSAVE"
    Warning: No output dependent on input pin "uP_PC6"
    Warning: No output dependent on input pin "LCD_MOD"
    Warning: No output dependent on input pin "LCD_SPL"
    Warning: No output dependent on input pin "LCD_D[16]"
    Warning: No output dependent on input pin "LCD_D[17]"
Info: Implemented 87 device resources after synthesis - the final resource count might be different
    Info: Implemented 33 input pins
    Info: Implemented 27 output pins
    Info: Implemented 27 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 23 warnings
    Info: Processing ended: Tue May 29 16:51:18 2007
    Info: Elapsed time: 00:00:02