cpld_for_lcd.fit.summary

一个VEILOG HDL程序

Flow Status : Successful - Tue May 29 16:51:21 2007
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : cpld_for_lcd
Top-level Entity Name : cpld_for_lcd
Family : MAX3000A
Device : EPM3128ATC100-10
Timing Models : Final
Met timing requirements : N/A
Total macrocells : 27 / 128 ( 21 % )
Total pins : 64 / 80 ( 80 % )