sintab_altera.fit.rpt

在利用Verilog在FPGA平台上输出正弦波

; Weak Pull-Up Resistor                                ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                            ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                   ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/Cyclone II       ; Auto                           ; Auto                           ;
; Auto Delay Chains                                    ; On                             ; On                             ;
; Auto Merge PLLs                                      ; On                             ; On                             ;
; Fitter Effort                                        ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                      ; Normal                         ; Normal                         ;
; Auto Global Clock                                    ; On                             ; On                             ;
; Auto Global Register Control Signals                 ; On                             ; On                             ;
+------------------------------------------------------+--------------------------------+--------------------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Active Serial            ;
; Error detection CRC                          ; Off                      ;
; Reserve nCEO pin after configuration         ; As output driving ground ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in E:/Coding/Sintab_Altera/Sintab_Altera.fit.eqn.


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/Coding/Sintab_Altera/Sintab_Altera.pin.


+------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                          ;
+---------------------------------------------+--------------------------+
; Resource                                    ; Usage                    ;
+---------------------------------------------+--------------------------+
; Total logic elements                        ; 11 / 50,528 ( < 1 % )    ;
;     -- Combinational with no register       ; 1                        ;
;     -- Register only                        ; 0                        ;
;     -- Combinational with a register        ; 10                       ;
;                                             ;                          ;
; Logic element usage by number of LUT inputs ;                          ;
;     -- 4 input functions                    ; 0                        ;
;     -- 3 input functions                    ; 0                        ;
;     -- <=2 input functions                  ; 11                       ;
;     -- Register only                        ; 0                        ;
;         -- Combinational cells for routing  ; 0                        ;
;                                             ;                          ;
; Logic elements by mode                      ;                          ;
;     -- normal mode                          ; 2                        ;
;     -- arithmetic mode                      ; 9                        ;
;                                             ;                          ;
; Total registers                             ; 10 / 50,528 ( < 1 % )    ;
; Total LABs                                  ; 2 / 3,158 ( < 1 % )      ;
; User inserted logic elements                ; 0                        ;
; Virtual pins                                ; 0                        ;
; I/O pins                                    ; 26 / 294 ( 9 % )         ;
;     -- Clock pins                           ; 1 / 8 ( 13 % )           ;
; Global signals                              ; 2                        ;
; M4Ks                                        ; 4 / 129 ( 3 % )          ;
; Total memory bits                           ; 14,336 / 594,432 ( 2 % ) ;
; Total RAM block bits                        ; 18,432 / 594,432 ( 3 % ) ;
; Embedded Multiplier 9-bit elements          ; 0 / 172 ( 0 % )          ;
; PLLs                                        ; 0 / 4 ( 0 % )            ;
; Global clocks                               ; 2 / 16 ( 13 % )          ;
; Maximum fan-out node                        ; sys_clk~clkctrl          ;
; Maximum fan-out                             ; 14                       ;
; Highest non-global fan-out signal           ; ~GND                     ;
; Highest non-global fan-out                  ; 14                       ;
; Total fan-out                               ; 123                      ;
; Average fan-out                             ; 2.20                     ;
+---------------------------------------------+--------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                    ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; rst_n   ; M2    ; 1        ; 0            ; 22           ; 3           ; 1                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; LVTTL        ; Off         ; Fitter               ;
; sys_clk ; M1    ; 1        ; 0            ; 22           ; 2           ; 1                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; LVTTL        ; Off         ; Fitter               ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                                     ;