📄 sintab_altera.map.rpt
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; -- <=2 input functions ; 11 ;
; -- Combinational cells for routing ; 0 ;
; Logic elements by mode ; ;
; -- normal mode ; 2 ;
; -- arithmetic mode ; 9 ;
; Total registers ; 10 ;
; I/O pins ; 26 ;
; Total memory bits ; 14336 ;
; Maximum fan-out node ; sys_clk ;
; Maximum fan-out ; 24 ;
; Total fan-out ; 241 ;
; Average fan-out ; 3.95 ;
+---------------------------------------------+---------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------+
; |Sintab_Altera ; 11 (11) ; 10 (10) ; 14336 ; 0 ; 0 ; 0 ; 26 ; 0 ; |Sintab_Altera ;
; |sintab:sintab1| ; 0 (0) ; 0 (0) ; 14336 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Sintab_Altera|sintab:sintab1 ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 14336 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Sintab_Altera|sintab:sintab1|altsyncram:altsyncram_component ;
; |altsyncram_a851:auto_generated| ; 0 (0) ; 0 (0) ; 14336 ; 0 ; 0 ; 0 ; 0 ; 0 ; |Sintab_Altera|sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+-------+------------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+-------+------------+
; sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 1024 ; 14 ; -- ; -- ; 14336 ; sintab.mif ;
+------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+-------+------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 10 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 10 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------+
; Source assignments for sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------------+
; Assignment ; Value ; from ; to ;
+---------------------------------+--------------------+------+----------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+----------------------------------------+
+---------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sintab:sintab1|altsyncram:altsyncram_component ;
+------------------------------------+-----------------+--------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+-----------------+--------------------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; OPERATION_MODE ; SINGLE_PORT ; Untyped ;
; WIDTH_A ; 14 ; Integer ;
; WIDTHAD_A ; 10 ; Integer ;
; NUMWORDS_A ; 1024 ; Integer ;
; OUTDATA_REG_A ; CLOCK0 ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Integer ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; INIT_FILE ; sintab.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; CBXI_PARAMETER ; altsyncram_a851 ; Untyped ;
+------------------------------------+-----------------+--------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/Coding/Sintab_Altera/Sintab_Altera.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Fri Jul 06 15:36:47 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Sintab_Altera -c Sintab_Altera
Info: Found 1 design units, including 1 entities, in source file Sintab_Altera.v
Info: Found entity 1: Sintab_Altera
Info: Elaborating entity "Sintab_Altera" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at Sintab_Altera.v(17): truncated value with size 32 to match size of target (10)
Warning: Using design file sintab.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: sintab
Info: Elaborating entity "sintab" for hierarchy "sintab:sintab1"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf
Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "sintab:sintab1|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_a851.tdf
Info: Found entity 1: altsyncram_a851
Info: Elaborating entity "altsyncram_a851" for hierarchy "sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated"
Warning: Port "#2" on the entity instantiation of "sintab1" is connected to a signal of width 32. The formal width of the signal in the module is 14. Extra bits will be driven by GND.
Warning: Port "#3" on the entity instantiation of "sintab1" is connected to a signal of width 32. The formal width of the signal in the module is 1. Extra bits will be driven by GND.
Info: Implemented 51 device resources after synthesis - the final resource count might be different
Info: Implemented 2 input pins
Info: Implemented 24 output pins
Info: Implemented 11 logic cells
Info: Implemented 14 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
Info: Processing ended: Fri Jul 06 15:36:50 2007
Info: Elapsed time: 00:00:04
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