sintab_altera.tan.qmsg

在利用Verilog在FPGA平台上输出正弦波

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "sys_clk memory memory sintab:sintab1\|altsyncram:altsyncram_component\|altsyncram_a851:auto_generated\|ram_block1a4~porta_address_reg0 sintab:sintab1\|altsyncram:altsyncram_component\|altsyncram_a851:auto_generated\|q_a\[11\] 163.03 MHz Internal " "Info: Clock \"sys_clk\" Internal fmax is restricted to 163.03 MHz between source memory \"sintab:sintab1\|altsyncram:altsyncram_component\|altsyncram_a851:auto_generated\|ram_block1a4~porta_address_reg0\" and destination memory \"sintab:sintab1\|altsyncram:altsyncram_component\|altsyncram_a851:auto_generated\|q_a\[11\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "3.067 ns 3.067 ns 6.134 ns " "Info: fmax restricted to Clock High delay (3.067 ns) plus Clock Low delay (3.067 ns) : restricted to 6.134 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.641 ns + Longest memory memory " "Info: + Longest memory to memory delay is 3.641 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sintab:sintab1\|altsyncram:altsyncram_component\|altsyncram_a851:auto_generated\|ram_block1a4~porta_address_reg0 1 MEM M4K_X43_Y34 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X43_Y34; Fanout = 2; MEM Node = 'sintab:sintab1\|altsyncram:altsyncram_component\|altsyncram_a851:auto_generated\|ram_block1a4~porta_address_reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Sintab_Altera" "UNKNOWN" "V1" "E:/Coding/Sintab_Altera/db/Sintab_Altera.quartus_db" { Floorplan "E:/Coding/Sintab_Altera/" "" "" { sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|ram_block1a4~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_a851.tdf" "" { Text "E:/Coding/Sintab_Altera/db/altsyncram_a851.tdf" 129 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.641 ns) 3.641 ns sintab:sintab1\|altsyncram:altsyncram_component\|altsyncram_a851:auto_generated\|q_a\[11\] 2 MEM M4K_X43_Y34 1 " "Info: 2: + IC(0.000 ns) + CELL(3.641 ns) = 3.641 ns; Loc. = M4K_X43_Y34; Fanout = 1; MEM Node = 'sintab:sintab1\|altsyncram:altsyncram_component\|altsyncram_a851:auto_generated\|q_a\[11\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Sintab_Altera" "UNKNOWN" "V1" "E:/Coding/Sintab_Altera/db/Sintab_Altera.quartus_db" { Floorplan "E:/Coding/Sintab_Altera/" "" "3.641 ns" { sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|ram_block1a4~porta_address_reg0 sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[11] } "NODE_NAME" } "" } } { "db/altsyncram_a851.tdf" "" { Text "E:/Coding/Sintab_Altera/db/altsyncram_a851.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.641 ns ( 100.00 % ) " "Info: Total cell delay = 3.641 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Sintab_Altera" "UNKNOWN" "V1" "E:/Coding/Sintab_Altera/db/Sintab_Altera.quartus_db" { Floorplan "E:/Coding/Sintab_Altera/" "" "3.641 ns" { sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|ram_block1a4~porta_address_reg0 sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[11] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.641 ns" { sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|ram_block1a4~porta_address_reg0 sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[11] } { 0.000ns 0.000ns } { 0.000ns 3.641ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.020 ns - Smallest " "Info: - Smallest clock skew is -0.020 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clk destination 3.209 ns + Shortest memory " "Info: + Shortest clock path from clock \"sys_clk\" to destination memory is 3.209 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.080 ns) 1.080 ns sys_clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.080 ns) = 1.080 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'sys_clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Sintab_Altera" "UNKNOWN" "V1" "E:/Coding/Sintab_Altera/db/Sintab_Altera.quartus_db" { Floorplan "E:/Coding/Sintab_Altera/" "" "" { sys_clk } "NODE_NAME" } "" } } { "Sintab_Altera.v" "" { Text "E:/Coding/Sintab_Altera/Sintab_Altera.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.137 ns) + CELL(0.000 ns) 1.217 ns sys_clk~clkctrl 2 COMB CLKCTRL_G3 92 " "Info: 2: + IC(0.137 ns) + CELL(0.000 ns) = 1.217 ns; Loc. = CLKCTRL_G3; Fanout = 92; COMB Node = 'sys_clk~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Sintab_Altera" "UNKNOWN" "V1" "E:/Coding/Sintab_Altera/db/Sintab_Altera.quartus_db" { Floorplan "E:/Coding/Sintab_Altera/" "" "0.137 ns" { sys_clk sys_clk~clkctrl } "NODE_NAME" } "" } } { "Sintab_Altera.v" "" { Text "E:/Coding/Sintab_Altera/Sintab_Altera.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.177 ns) + CELL(0.815 ns) 3.209 ns sintab:sintab1\|altsyncram:altsyncram_component\|altsyncram_a851:auto_generated\|q_a\[11\] 3 MEM M4K_X43_Y34 1 " "Info: 3: + IC(1.177 ns) + CELL(0.815 ns) = 3.209 ns; Loc. = M4K_X43_Y34; Fanout = 1; MEM Node = 'sintab:sintab1\|altsyncram:altsyncram_component\|altsyncram_a851:auto_generated\|q_a\[11\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Sintab_Altera" "UNKNOWN" "V1" "E:/Coding/Sintab_Altera/db/Sintab_Altera.quartus_db" { Floorplan "E:/Coding/Sintab_Altera/" "" "1.992 ns" { sys_clk~clkctrl sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[11] } "NODE_NAME" } "" } } { "db/altsyncram_a851.tdf" "" { Text "E:/Coding/Sintab_Altera/db/altsyncram_a851.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.895 ns ( 59.05 % ) " "Info: Total cell delay = 1.895 ns ( 59.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.314 ns ( 40.95 % ) " "Info: Total interconnect delay = 1.314 ns ( 40.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Sintab_Altera" "UNKNOWN" "V1" "E:/Coding/Sintab_Altera/db/Sintab_Altera.quartus_db" { Floorplan "E:/Coding/Sintab_Altera/" "" "3.209 ns" { sys_clk sys_clk~clkctrl sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[11] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.209 ns" { sys_clk sys_clk~combout sys_clk~clkctrl sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[11] } { 0.000ns 0.000ns 0.137ns 1.177ns } { 0.000ns 1.080ns 0.000ns 0.815ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clk source 3.229 ns - Longest memory " "Info: - Longest clock path from clock \"sys_clk\" to source memory is 3.229 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.080 ns) 1.080 ns sys_clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.080 ns) = 1.080 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'sys_clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Sintab_Altera" "UNKNOWN" "V1" "E:/Coding/Sintab_Altera/db/Sintab_Altera.quartus_db" { Floorplan "E:/Coding/Sintab_Altera/" "" "" { sys_clk } "NODE_NAME" } "" } } { "Sintab_Altera.v" "" { Text "E:/Coding/Sintab_Altera/Sintab_Altera.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.137 ns) + CELL(0.000 ns) 1.217 ns sys_clk~clkctrl 2 COMB CLKCTRL_G3 92 " "Info: 2: + IC(0.137 ns) + CELL(0.000 ns) = 1.217 ns; Loc. = CLKCTRL_G3; Fanout = 92; COMB Node = 'sys_clk~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Sintab_Altera" "UNKNOWN" "V1" "E:/Coding/Sintab_Altera/db/Sintab_Altera.quartus_db" { Floorplan "E:/Coding/Sintab_Altera/" "" "0.137 ns" { sys_clk sys_clk~clkctrl } "NODE_NAME" } "" } } { "Sintab_Altera.v" "" { Text "E:/Coding/Sintab_Altera/Sintab_Altera.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.177 ns) + CELL(0.835 ns) 3.229 ns sintab:sintab1\|altsyncram:altsyncram_component\|altsyncram_a851:auto_generated\|ram_block1a4~porta_address_reg0 3 MEM M4K_X43_Y34 2 " "Info: 3: + IC(1.177 ns) + CELL(0.835 ns) = 3.229 ns; Loc. = M4K_X43_Y34; Fanout = 2; MEM Node = 'sintab:sintab1\|altsyncram:altsyncram_component\|altsyncram_a851:auto_generated\|ram_block1a4~porta_address_reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Sintab_Altera" "UNKNOWN" "V1" "E:/Coding/Sintab_Altera/db/Sintab_Altera.quartus_db" { Floorplan "E:/Coding/Sintab_Altera/" "" "2.012 ns" { sys_clk~clkctrl sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|ram_block1a4~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_a851.tdf" "" { Text "E:/Coding/Sintab_Altera/db/altsyncram_a851.tdf" 129 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.915 ns ( 59.31 % ) " "Info: Total cell delay = 1.915 ns ( 59.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.314 ns ( 40.69 % ) " "Info: Total interconnect delay = 1.314 ns ( 40.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Sintab_Altera" "UNKNOWN" "V1" "E:/Coding/Sintab_Altera/db/Sintab_Altera.quartus_db" { Floorplan "E:/Coding/Sintab_Altera/" "" "3.229 ns" { sys_clk sys_clk~clkctrl sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|ram_block1a4~porta_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.229 ns" { sys_clk sys_clk~combout sys_clk~clkctrl sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|ram_block1a4~porta_address_reg0 } { 0.000ns 0.000ns 0.137ns 1.177ns } { 0.000ns 1.080ns 0.000ns 0.835ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Sintab_Altera" "UNKNOWN" "V1" "E:/Coding/Sintab_Altera/db/Sintab_Altera.quartus_db" { Floorplan "E:/Coding/Sintab_Altera/" "" "3.209 ns" { sys_clk sys_clk~clkctrl sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[11] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.209 ns" { sys_clk sys_clk~combout sys_clk~clkctrl sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[11] } { 0.000ns 0.000ns 0.137ns 1.177ns } { 0.000ns 1.080ns 0.000ns 0.815ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Sintab_Altera" "UNKNOWN" "V1" "E:/Coding/Sintab_Altera/db/Sintab_Altera.quartus_db" { Floorplan "E:/Coding/Sintab_Altera/" "" "3.229 ns" { sys_clk sys_clk~clkctrl sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|ram_block1a4~porta_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.229 ns" { sys_clk sys_clk~combout sys_clk~clkctrl sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|ram_block1a4~porta_address_reg0 } { 0.000ns 0.000ns 0.137ns 1.177ns } { 0.000ns 1.080ns 0.000ns 0.835ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" {  } { { "db/altsyncram_a851.tdf" "" { Text "E:/Coding/Sintab_Altera/db/altsyncram_a851.tdf" 129 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns + " "Info: + Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_a851.tdf" "" { Text "E:/Coding/Sintab_Altera/db/altsyncram_a851.tdf" 41 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Sintab_Altera" "UNKNOWN" "V1" "E:/Coding/Sintab_Altera/db/Sintab_Altera.quartus_db" { Floorplan "E:/Coding/Sintab_Altera/" "" "3.641 ns" { sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|ram_block1a4~porta_address_reg0 sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[11] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.641 ns" { sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|ram_block1a4~porta_address_reg0 sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[11] } { 0.000ns 0.000ns } { 0.000ns 3.641ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Sintab_Altera" "UNKNOWN" "V1" "E:/Coding/Sintab_Altera/db/Sintab_Altera.quartus_db" { Floorplan "E:/Coding/Sintab_Altera/" "" "3.209 ns" { sys_clk sys_clk~clkctrl sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[11] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.209 ns" { sys_clk sys_clk~combout sys_clk~clkctrl sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[11] } { 0.000ns 0.000ns 0.137ns 1.177ns } { 0.000ns 1.080ns 0.000ns 0.815ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Sintab_Altera" "UNKNOWN" "V1" "E:/Coding/Sintab_Altera/db/Sintab_Altera.quartus_db" { Floorplan "E:/Coding/Sintab_Altera/" "" "3.229 ns" { sys_clk sys_clk~clkctrl sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|ram_block1a4~porta_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.229 ns" { sys_clk sys_clk~combout sys_clk~clkctrl sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|ram_block1a4~porta_address_reg0 } { 0.000ns 0.000ns 0.137ns 1.177ns } { 0.000ns 1.080ns 0.000ns 0.835ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Sintab_Altera" "UNKNOWN" "V1" "E:/Coding/Sintab_Altera/db/Sintab_Altera.quartus_db" { Floorplan "E:/Coding/Sintab_Altera/" "" "" { sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[11] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[11] } { 0.000ns } { 0.109ns } } } { "db/altsyncram_a851.tdf" "" { Text "E:/Coding/Sintab_Altera/db/altsyncram_a851.tdf" 41 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "sys_clk sin_output\[5\] sintab:sintab1\|altsyncram:altsyncram_component\|altsyncram_a851:auto_generated\|q_a\[5\] 11.416 ns memory " "Info: tco from clock \"sys_clk\" to destination pin \"sin_output\[5\]\" through memory \"sintab:sintab1\|altsyncram:altsyncram_component\|altsyncram_a851:auto_generated\|q_a\[5\]\" is 11.416 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clk source 3.197 ns + Longest memory " "Info: + Longest clock path from clock \"sys_clk\" to source memory is 3.197 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.080 ns) 1.080 ns sys_clk 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.080 ns) = 1.080 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'sys_clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Sintab_Altera" "UNKNOWN" "V1" "E:/Coding/Sintab_Altera/db/Sintab_Altera.quartus_db" { Floorplan "E:/Coding/Sintab_Altera/" "" "" { sys_clk } "NODE_NAME" } "" } } { "Sintab_Altera.v" "" { Text "E:/Coding/Sintab_Altera/Sintab_Altera.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.137 ns) + CELL(0.000 ns) 1.217 ns sys_clk~clkctrl 2 COMB CLKCTRL_G3 92 " "Info: 2: + IC(0.137 ns) + CELL(0.000 ns) = 1.217 ns; Loc. = CLKCTRL_G3; Fanout = 92; COMB Node = 'sys_clk~clkctrl'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Sintab_Altera" "UNKNOWN" "V1" "E:/Coding/Sintab_Altera/db/Sintab_Altera.quartus_db" { Floorplan "E:/Coding/Sintab_Altera/" "" "0.137 ns" { sys_clk sys_clk~clkctrl } "NODE_NAME" } "" } } { "Sintab_Altera.v" "" { Text "E:/Coding/Sintab_Altera/Sintab_Altera.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.165 ns) + CELL(0.815 ns) 3.197 ns sintab:sintab1\|altsyncram:altsyncram_component\|altsyncram_a851:auto_generated\|q_a\[5\] 3 MEM M4K_X43_Y33 1 " "Info: 3: + IC(1.165 ns) + CELL(0.815 ns) = 3.197 ns; Loc. = M4K_X43_Y33; Fanout = 1; MEM Node = 'sintab:sintab1\|altsyncram:altsyncram_component\|altsyncram_a851:auto_generated\|q_a\[5\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Sintab_Altera" "UNKNOWN" "V1" "E:/Coding/Sintab_Altera/db/Sintab_Altera.quartus_db" { Floorplan "E:/Coding/Sintab_Altera/" "" "1.980 ns" { sys_clk~clkctrl sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[5] } "NODE_NAME" } "" } } { "db/altsyncram_a851.tdf" "" { Text "E:/Coding/Sintab_Altera/db/altsyncram_a851.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.895 ns ( 59.27 % ) " "Info: Total cell delay = 1.895 ns ( 59.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.302 ns ( 40.73 % ) " "Info: Total interconnect delay = 1.302 ns ( 40.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Sintab_Altera" "UNKNOWN" "V1" "E:/Coding/Sintab_Altera/db/Sintab_Altera.quartus_db" { Floorplan "E:/Coding/Sintab_Altera/" "" "3.197 ns" { sys_clk sys_clk~clkctrl sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.197 ns" { sys_clk sys_clk~combout sys_clk~clkctrl sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[5] } { 0.000ns 0.000ns 0.137ns 1.165ns } { 0.000ns 1.080ns 0.000ns 0.815ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" {  } { { "db/altsyncram_a851.tdf" "" { Text "E:/Coding/Sintab_Altera/db/altsyncram_a851.tdf" 41 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.959 ns + Longest memory pin " "Info: + Longest memory to pin delay is 7.959 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.109 ns) 0.109 ns sintab:sintab1\|altsyncram:altsyncram_component\|altsyncram_a851:auto_generated\|q_a\[5\] 1 MEM M4K_X43_Y33 1 " "Info: 1: + IC(0.000 ns) + CELL(0.109 ns) = 0.109 ns; Loc. = M4K_X43_Y33; Fanout = 1; MEM Node = 'sintab:sintab1\|altsyncram:altsyncram_component\|altsyncram_a851:auto_generated\|q_a\[5\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Sintab_Altera" "UNKNOWN" "V1" "E:/Coding/Sintab_Altera/db/Sintab_Altera.quartus_db" { Floorplan "E:/Coding/Sintab_Altera/" "" "" { sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[5] } "NODE_NAME" } "" } } { "db/altsyncram_a851.tdf" "" { Text "E:/Coding/Sintab_Altera/db/altsyncram_a851.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.644 ns) + CELL(3.206 ns) 7.959 ns sin_output\[5\] 2 PIN PIN_AA12 0 " "Info: 2: + IC(4.644 ns) + CELL(3.206 ns) = 7.959 ns; Loc. = PIN_AA12; Fanout = 0; PIN Node = 'sin_output\[5\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Sintab_Altera" "UNKNOWN" "V1" "E:/Coding/Sintab_Altera/db/Sintab_Altera.quartus_db" { Floorplan "E:/Coding/Sintab_Altera/" "" "7.850 ns" { sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[5] sin_output[5] } "NODE_NAME" } "" } } { "Sintab_Altera.v" "" { Text "E:/Coding/Sintab_Altera/Sintab_Altera.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.315 ns ( 41.65 % ) " "Info: Total cell delay = 3.315 ns ( 41.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.644 ns ( 58.35 % ) " "Info: Total interconnect delay = 4.644 ns ( 58.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Sintab_Altera" "UNKNOWN" "V1" "E:/Coding/Sintab_Altera/db/Sintab_Altera.quartus_db" { Floorplan "E:/Coding/Sintab_Altera/" "" "7.959 ns" { sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[5] sin_output[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.959 ns" { sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[5] sin_output[5] } { 0.000ns 4.644ns } { 0.109ns 3.206ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Sintab_Altera" "UNKNOWN" "V1" "E:/Coding/Sintab_Altera/db/Sintab_Altera.quartus_db" { Floorplan "E:/Coding/Sintab_Altera/" "" "3.197 ns" { sys_clk sys_clk~clkctrl sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.197 ns" { sys_clk sys_clk~combout sys_clk~clkctrl sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[5] } { 0.000ns 0.000ns 0.137ns 1.165ns } { 0.000ns 1.080ns 0.000ns 0.815ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Sintab_Altera" "UNKNOWN" "V1" "E:/Coding/Sintab_Altera/db/Sintab_Altera.quartus_db" { Floorplan "E:/Coding/Sintab_Altera/" "" "7.959 ns" { sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[5] sin_output[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.959 ns" { sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[5] sin_output[5] } { 0.000ns 4.644ns } { 0.109ns 3.206ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jul 06 15:37:26 2007 " "Info: Processing ended: Fri Jul 06 15:37:26 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}