sintab_altera.map.qmsg

在利用Verilog在FPGA平台上输出正弦波

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jul 06 15:36:47 2007 " "Info: Processing started: Fri Jul 06 15:36:47 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Sintab_Altera -c Sintab_Altera " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Sintab_Altera -c Sintab_Altera" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Sintab_Altera.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Sintab_Altera.v" { { "Info" "ISGN_ENTITY_NAME" "1 Sintab_Altera " "Info: Found entity 1: Sintab_Altera" {  } { { "Sintab_Altera.v" "" { Text "E:/Coding/Sintab_Altera/Sintab_Altera.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Sintab_Altera " "Info: Elaborating entity \"Sintab_Altera\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 Sintab_Altera.v(17) " "Warning (10230): Verilog HDL assignment warning at Sintab_Altera.v(17): truncated value with size 32 to match size of target (10)" {  } { { "Sintab_Altera.v" "" { Text "E:/Coding/Sintab_Altera/Sintab_Altera.v" 17 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "sintab.v 1 1 " "Warning: Using design file sintab.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sintab " "Info: Found entity 1: sintab" {  } { { "sintab.v" "" { Text "E:/Coding/Sintab_Altera/sintab.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sintab sintab:sintab1 " "Info: Elaborating entity \"sintab\" for hierarchy \"sintab:sintab1\"" {  } { { "Sintab_Altera.v" "sintab1" { Text "E:/Coding/Sintab_Altera/Sintab_Altera.v" 22 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram sintab:sintab1\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"sintab:sintab1\|altsyncram:altsyncram_component\"" {  } { { "sintab.v" "altsyncram_component" { Text "E:/Coding/Sintab_Altera/sintab.v" 52 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_a851.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_a851.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_a851 " "Info: Found entity 1: altsyncram_a851" {  } { { "db/altsyncram_a851.tdf" "" { Text "E:/Coding/Sintab_Altera/db/altsyncram_a851.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_a851 sintab:sintab1\|altsyncram:altsyncram_component\|altsyncram_a851:auto_generated " "Info: Elaborating entity \"altsyncram_a851\" for hierarchy \"sintab:sintab1\|altsyncram:altsyncram_component\|altsyncram_a851:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT" "#2 sintab1 32 14 " "Warning: Port \"#2\" on the entity instantiation of \"sintab1\" is connected to a signal of width 32. The formal width of the signal in the module is 14.  Extra bits will be driven by GND." {  } { { "Sintab_Altera.v" "sintab1" { Text "E:/Coding/Sintab_Altera/Sintab_Altera.v" 22 -1 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 0 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT" "#3 sintab1 32 1 " "Warning: Port \"#3\" on the entity instantiation of \"sintab1\" is connected to a signal of width 32. The formal width of the signal in the module is 1.  Extra bits will be driven by GND." {  } { { "Sintab_Altera.v" "sintab1" { Text "E:/Coding/Sintab_Altera/Sintab_Altera.v" 22 -1 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "51 " "Info: Implemented 51 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "24 " "Info: Implemented 24 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "11 " "Info: Implemented 11 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "14 " "Info: Implemented 14 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jul 06 15:36:50 2007 " "Info: Processing ended: Fri Jul 06 15:36:50 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}