📄 sintab_altera.sim.rpt
字号:
; |Sintab_Altera|sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[1] ; |Sintab_Altera|sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[5] ; portadataout1 ;
; |Sintab_Altera|sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[1] ; |Sintab_Altera|sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[10] ; portadataout2 ;
; |Sintab_Altera|sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[1] ; |Sintab_Altera|sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[13] ; portadataout3 ;
; |Sintab_Altera|sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[2] ; |Sintab_Altera|sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[2] ; portadataout0 ;
; |Sintab_Altera|sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[2] ; |Sintab_Altera|sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[3] ; portadataout1 ;
; |Sintab_Altera|sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[2] ; |Sintab_Altera|sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[6] ; portadataout2 ;
; |Sintab_Altera|sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[2] ; |Sintab_Altera|sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[12] ; portadataout3 ;
; |Sintab_Altera|sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[4] ; |Sintab_Altera|sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[4] ; portadataout0 ;
; |Sintab_Altera|sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[4] ; |Sintab_Altera|sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|q_a[11] ; portadataout1 ;
; |Sintab_Altera|counter[0]~reg0 ; |Sintab_Altera|counter[0]~reg0 ; regout ;
; |Sintab_Altera|counter[1]~reg0 ; |Sintab_Altera|counter[1]~reg0 ; regout ;
; |Sintab_Altera|counter[2]~reg0 ; |Sintab_Altera|counter[2]~reg0 ; regout ;
; |Sintab_Altera|counter[3]~reg0 ; |Sintab_Altera|counter[3]~reg0 ; regout ;
; |Sintab_Altera|counter[4]~reg0 ; |Sintab_Altera|counter[4]~reg0 ; regout ;
; |Sintab_Altera|counter[5]~reg0 ; |Sintab_Altera|counter[5]~reg0 ; regout ;
; |Sintab_Altera|counter[6]~reg0 ; |Sintab_Altera|counter[6]~reg0 ; regout ;
; |Sintab_Altera|counter[7]~reg0 ; |Sintab_Altera|counter[7]~reg0 ; regout ;
; |Sintab_Altera|counter[8]~reg0 ; |Sintab_Altera|counter[8]~reg0 ; regout ;
; |Sintab_Altera|counter[9]~reg0 ; |Sintab_Altera|counter[9]~reg0 ; regout ;
; |Sintab_Altera|counter[0]~90 ; |Sintab_Altera|counter[0]~90 ; combout ;
; |Sintab_Altera|counter[0]~90 ; |Sintab_Altera|counter[0]~91 ; cout ;
; |Sintab_Altera|counter[1]~92 ; |Sintab_Altera|counter[1]~92 ; combout ;
; |Sintab_Altera|counter[1]~92 ; |Sintab_Altera|counter[1]~93 ; cout ;
; |Sintab_Altera|counter[2]~94 ; |Sintab_Altera|counter[2]~94 ; combout ;
; |Sintab_Altera|counter[2]~94 ; |Sintab_Altera|counter[2]~95 ; cout ;
; |Sintab_Altera|counter[3]~96 ; |Sintab_Altera|counter[3]~96 ; combout ;
; |Sintab_Altera|counter[3]~96 ; |Sintab_Altera|counter[3]~97 ; cout ;
; |Sintab_Altera|counter[4]~98 ; |Sintab_Altera|counter[4]~98 ; combout ;
; |Sintab_Altera|counter[4]~98 ; |Sintab_Altera|counter[4]~99 ; cout ;
; |Sintab_Altera|counter[5]~100 ; |Sintab_Altera|counter[5]~100 ; combout ;
; |Sintab_Altera|counter[5]~100 ; |Sintab_Altera|counter[5]~101 ; cout ;
; |Sintab_Altera|counter[6]~102 ; |Sintab_Altera|counter[6]~102 ; combout ;
; |Sintab_Altera|counter[6]~102 ; |Sintab_Altera|counter[6]~103 ; cout ;
; |Sintab_Altera|counter[7]~104 ; |Sintab_Altera|counter[7]~104 ; combout ;
; |Sintab_Altera|counter[7]~104 ; |Sintab_Altera|counter[7]~105 ; cout ;
; |Sintab_Altera|counter[8]~106 ; |Sintab_Altera|counter[8]~106 ; combout ;
; |Sintab_Altera|counter[8]~106 ; |Sintab_Altera|counter[8]~107 ; cout ;
; |Sintab_Altera|counter[9]~108 ; |Sintab_Altera|counter[9]~108 ; combout ;
; |Sintab_Altera|sys_clk ; |Sintab_Altera|sys_clk ; combout ;
; |Sintab_Altera|rst_n ; |Sintab_Altera|rst_n ; combout ;
; |Sintab_Altera|sin_output[0] ; |Sintab_Altera|sin_output[0] ; padio ;
; |Sintab_Altera|sin_output[1] ; |Sintab_Altera|sin_output[1] ; padio ;
; |Sintab_Altera|sin_output[2] ; |Sintab_Altera|sin_output[2] ; padio ;
; |Sintab_Altera|sin_output[3] ; |Sintab_Altera|sin_output[3] ; padio ;
; |Sintab_Altera|sin_output[4] ; |Sintab_Altera|sin_output[4] ; padio ;
; |Sintab_Altera|sin_output[5] ; |Sintab_Altera|sin_output[5] ; padio ;
; |Sintab_Altera|sin_output[6] ; |Sintab_Altera|sin_output[6] ; padio ;
; |Sintab_Altera|sin_output[7] ; |Sintab_Altera|sin_output[7] ; padio ;
; |Sintab_Altera|sin_output[8] ; |Sintab_Altera|sin_output[8] ; padio ;
; |Sintab_Altera|sin_output[9] ; |Sintab_Altera|sin_output[9] ; padio ;
; |Sintab_Altera|sin_output[10] ; |Sintab_Altera|sin_output[10] ; padio ;
; |Sintab_Altera|sin_output[11] ; |Sintab_Altera|sin_output[11] ; padio ;
; |Sintab_Altera|sin_output[12] ; |Sintab_Altera|sin_output[12] ; padio ;
; |Sintab_Altera|sin_output[13] ; |Sintab_Altera|sin_output[13] ; padio ;
; |Sintab_Altera|counter[0] ; |Sintab_Altera|counter[0] ; padio ;
; |Sintab_Altera|counter[1] ; |Sintab_Altera|counter[1] ; padio ;
; |Sintab_Altera|counter[2] ; |Sintab_Altera|counter[2] ; padio ;
; |Sintab_Altera|counter[3] ; |Sintab_Altera|counter[3] ; padio ;
; |Sintab_Altera|counter[4] ; |Sintab_Altera|counter[4] ; padio ;
; |Sintab_Altera|counter[5] ; |Sintab_Altera|counter[5] ; padio ;
; |Sintab_Altera|counter[6] ; |Sintab_Altera|counter[6] ; padio ;
; |Sintab_Altera|counter[7] ; |Sintab_Altera|counter[7] ; padio ;
; |Sintab_Altera|counter[8] ; |Sintab_Altera|counter[8] ; padio ;
; |Sintab_Altera|counter[9] ; |Sintab_Altera|counter[9] ; padio ;
; |Sintab_Altera|sys_clk~clkctrl ; |Sintab_Altera|sys_clk~clkctrl ; outclk ;
; |Sintab_Altera|rst_n~clkctrl ; |Sintab_Altera|rst_n~clkctrl ; outclk ;
+-----------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+--------------------------------------------------------------+
; Missing 1-Value Coverage ;
+---------------------+---------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+---------------------+---------------------+------------------+
; |Sintab_Altera|~GND ; |Sintab_Altera|~GND ; combout ;
+---------------------+---------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+--------------------------------------------------------------+
; Missing 0-Value Coverage ;
+---------------------+---------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+---------------------+---------------------+------------------+
; |Sintab_Altera|~GND ; |Sintab_Altera|~GND ; combout ;
+---------------------+---------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Fri Jul 06 15:45:30 2007
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off Sintab_Altera -c Sintab_Altera
Info: Overwriting simulation input file with simulation results
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 98.61 %
Info: Number of transitions in simulation is 260208
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
Info: Processing ended: Fri Jul 06 15:45:36 2007
Info: Elapsed time: 00:00:06
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -