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📄 sintab_altera.vo

📁 在利用Verilog在FPGA平台上输出正弦波
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// synopsys translate_on

// atom is at M4K_X43_Y36
cycloneii_ram_block \sintab1|altsyncram_component|auto_generated|ram_block1a2 (
	.portawe(gnd),
	.portaaddrstall(gnd),
	.portbrewe(vcc),
	.portbaddrstall(gnd),
	.clk0(\sys_clk~clkctrl ),
	.clk1(gnd),
	.ena0(vcc),
	.ena1(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND ,\~GND ,\~GND ,\~GND }),
	.portaaddr({\counter[9]~reg0 ,\counter[8]~reg0 ,\counter[7]~reg0 ,\counter[6]~reg0 ,\counter[5]~reg0 ,\counter[4]~reg0 ,\counter[3]~reg0 ,\counter[2]~reg0 ,\counter[1]~reg0 ,\counter[0]~reg0 }),
	.portabyteenamasks(),
	.portbdatain(),
	.portbaddr(),
	.portbbyteenamasks(),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\sintab1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M4K";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|ALTSYNCRAM";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "sintab.mif";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 1024;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 14;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_in_clear = "none";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clear = "none";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clear = "none";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 1023;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 0;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 4;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 10;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 10;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 4;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a2 .safe_write = "err_on_2clk";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'hFAE99C8FAAD9CCBFAED9C8FFBEA9D9CC8FBFFAEAAE9DD9D99D9DD9DAAEAEFBFC8D9AEBFC9DEBFC9EB8DAB41341241342353064245354206035324710720761072254036621551044015512673045230563057413464235753206532076432107761100777333377445122305674530130206464646431031032103321100000000000112330123013013464646460203103547650322154477333377700116770123467023560235753246431475036503254037621551044015512673045227016702701742353060245354246035324314214314BAD8BE9CFBED9CFBEA9D8CFBFEAEAAD9DD9D99D9DD9EAAEAFFBF8CC9D9AEBFF8C9DEAFBCC9DAAF8C99EAF0;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0516637055263340512637004156263370400515516226266262262551510403726514036214036147254BECBEDBECBDCACF9BDBACABDF9FCACDB8EF8DF89EF8DDABFC99DEAAEFBBFEAAED98CFBADCFA9CFA8BECB9BDCA8ACDF9ACDF89BCDEF889EEFF888CCCC88BBAEDDCFA98BACFECFDF9B9B9B9BCEFCEFCDEFCCDEEFFFFFFFFFFFEEDCCFEDCFECFECB9B9B9B9FDFCEFCAB89AFCDDEABB88CCCC888FFEE988FEDCB98FDCA9FDCA8ACDB9BCEB8AFC9AFCDABFC89DEAAEFBBFEAAED99CFBADD8FE98FD8FE8BDCACF9FDBACABDB9FCACDBCEBDEBCEB4527416304126304156273040151552622626626226155150040733626514007362150433625507366150F;
// synopsys translate_on

// atom is at M4K_X43_Y34
cycloneii_ram_block \sintab1|altsyncram_component|auto_generated|ram_block1a4 (
	.portawe(gnd),
	.portaaddrstall(gnd),
	.portbrewe(vcc),
	.portbaddrstall(gnd),
	.clk0(\sys_clk~clkctrl ),
	.clk1(gnd),
	.ena0(vcc),
	.ena1(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND ,\~GND }),
	.portaaddr({\counter[9]~reg0 ,\counter[8]~reg0 ,\counter[7]~reg0 ,\counter[6]~reg0 ,\counter[5]~reg0 ,\counter[4]~reg0 ,\counter[3]~reg0 ,\counter[2]~reg0 ,\counter[1]~reg0 ,\counter[0]~reg0 }),
	.portabyteenamasks(),
	.portbdatain(),
	.portbaddr(),
	.portbbyteenamasks(),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\sintab1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M4K";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|ALTSYNCRAM";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "sintab.mif";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 1024;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 14;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_in_clear = "none";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clear = "none";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clear = "none";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 1023;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 0;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 2;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 10;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 10;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 2;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a4 .safe_write = "err_on_2clk";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'hBBBAEEEBBBBEEEEEFBBB91111111111044451104512EBAEBAFAFBFAFAFEAFEABFFEAA0000000155005405014105145104441111044411451414141501540000000000550150505051451044411110444114514105014054015500000002AAFFFAAFEAFEBEBFBEBEBAEBAE1144111444411111111111BBBBEEEEEFBBBAEEEBBB8444511144441111104446EEEEEEEEEEFBBBAEEFBAED14514505040505015015400155FFFFFFFEAAFFABFAFEBEFAEBAEFBBBEEEEFBBBEEBAEBEBEBEAFEABFFFFFFFFFFAAFEAFAFAFAEBAEFBBBEEEEFBBBEEBAEBEFAFEBFABFEAAFFFFFFFD55000550150141404141451451EEBBEEEBBBBEEEEEEEEEEE444411111044451114447;
// synopsys translate_on

// atom is at PIN_B9
cycloneii_io \sin_output[0]~I (
	.datain(\sintab1|altsyncram_component|auto_generated|q_a[0] ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(sin_output[0]));
// synopsys translate_off
defparam \sin_output[0]~I .operation_mode = "output";
defparam \sin_output[0]~I .input_register_mode = "none";
defparam \sin_output[0]~I .output_register_mode = "none";
defparam \sin_output[0]~I .oe_register_mode = "none";
defparam \sin_output[0]~I .input_async_reset = "none";
defparam \sin_output[0]~I .output_async_reset = "none";
defparam \sin_output[0]~I .oe_async_reset = "none";
defparam \sin_output[0]~I .input_sync_reset = "none";
defparam \sin_output[0]~I .output_sync_reset = "none";
defparam \sin_output[0]~I .oe_sync_reset = "none";
defparam \sin_output[0]~I .input_power_up = "low";
defparam \sin_output[0]~I .output_power_up = "low";
defparam \sin_output[0]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at PIN_F10
cycloneii_io \sin_output[1]~I (
	.datain(\sintab1|altsyncram_component|auto_generated|q_a[1] ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(sin_output[1]));
// synopsys translate_off
defparam \sin_output[1]~I .operation_mode = "output";
defparam \sin_output[1]~I .input_register_mode = "none";
defparam \sin_output[1]~I .output_register_mode = "none";
defparam \sin_output[1]~I .oe_register_mode = "none";
defparam \sin_output[1]~I .input_async_reset = "none";
defparam \sin_output[1]~I .output_async_reset = "none";
defparam \sin_output[1]~I .oe_async_reset = "none";
defparam \sin_output[1]~I .input_sync_reset = "none";
defparam \sin_output[1]~I .output_sync_reset = "none";
defparam \sin_output[1]~I .oe_sync_reset = "none";
defparam \sin_output[1]~I .input_power_up = "low";
defparam \sin_output[1]~I .output_power_up = "low";
defparam \sin_output[1]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at PIN_C10
cycloneii_io \sin_output[2]~I (
	.datain(\sintab1|altsyncram_component|auto_generated|q_a[2] ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(sin_output[2]));
// synopsys translate_off
defparam \sin_output[2]~I .operation_mode = "output";
defparam \sin_output[2]~I .input_register_mode = "none";
defparam \sin_output[2]~I .output_register_mode = "none";
defparam \sin_output[2]~I .oe_register_mode = "none";
defparam \sin_output[2]~I .input_async_reset = "none";
defparam \sin_output[2]~I .output_async_reset = "none";
defparam \sin_output[2]~I .oe_async_reset = "none";
defparam \sin_output[2]~I .input_sync_reset = "none";
defparam \sin_output[2]~I .output_sync_reset = "none";
defparam \sin_output[2]~I .oe_sync_reset = "none";
defparam \sin_output[2]~I .input_power_up = "low";
defparam \sin_output[2]~I .output_power_up = "low";
defparam \sin_output[2]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at PIN_E22
cycloneii_io \sin_output[3]~I (
	.datain(\sintab1|altsyncram_component|auto_generated|q_a[3] ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(sin_output[3]));
// synopsys translate_off
defparam \sin_output[3]~I .operation_mode = "output";
defparam \sin_output[3]~I .input_register_mode = "none";
defparam \sin_output[3]~I .output_register_mode = "none";
defparam \sin_output[3]~I .oe_register_mode = "none";
defparam \sin_output[3]~I .input_async_reset = "none";
defparam \sin_output[3]~I .output_async_reset = "none";
defparam \sin_output[3]~I .oe_async_reset = "none";
defparam \sin_output[3]~I .input_sync_reset = "none";
defparam \sin_output[3]~I .output_sync_reset = "none";
defparam \sin_output[3]~I .oe_sync_reset = "none";
defparam \sin_output[3]~I .input_power_up = "low";
defparam \sin_output[3]~I .output_power_up = "low";
defparam \sin_output[3]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at PIN_F22
cycloneii_io \sin_output[4]~I (
	.datain(\sintab1|altsyncram_component|auto_generated|q_a[4] ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(sin_output[4]));
// synopsys translate_off
defparam \sin_output[4]~I .operation_mode = "output";
defparam \sin_output[4]~I .input_register_mode = "none";
defparam \sin_output[4]~I .output_register_mode = "none";
defparam \sin_output[4]~I .oe_register_mode = "none";
defparam \sin_output[4]~I .input_async_reset = "none";
defparam \sin_output[4]~I .output_async_reset = "none";
defparam \sin_output[4]~I .oe_async_reset = "none";
defparam \sin_output[4]~I .input_sync_reset = "none";
defparam \sin_output[4]~I .output_sync_reset = "none";
defparam \sin_output[4]~I .oe_sync_reset = "none";
defparam \sin_output[4]~I .input_power_up = "low";
defparam \sin_output[4]~I .output_power_up = "low";
defparam \sin_output[4]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at PIN_AA12
cycloneii_io \sin_output[5]~I (
	.datain(\sintab1|altsyncram_component|auto_generated|q_a[5] ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(sin_output[5]));
// synopsys translate_off
defparam \sin_output[5]~I .operation_mode = "output";
defparam \sin_output[5]~I .input_register_mode = "none";
defparam \sin_output[5]~I .output_register_mode = "none";
defparam \sin_output[5]~I .oe_register_mode = "none";
defparam \sin_output[5]~I .input_async_reset = "none";
defparam \sin_output[5]~I .output_async_reset = "none";
defparam \sin_output[5]~I .oe_async_reset = "none";
defparam \sin_output[5]~I .input_sync_reset = "none";
defparam \sin_output[5]~I .output_sync_reset = "none";
defparam \sin_output[5]~I .oe_sync_reset = "none";
defparam \sin_output[5]~I .input_power_up = "low";
defparam \sin_output[5]~I .output_power_up = "low";
defparam \sin_output[5]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at PIN_A15
cycloneii_io \sin_output[6]~I (
	.datain(\sintab1|altsyncram_component|auto_generated|q_a[6] ),
	.oe(vcc),
12345

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