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📄 sintab_altera.vo

📁 在利用Verilog在FPGA平台上输出正弦波
💻 VO
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	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(\counter[2]~reg0 ));

// atom is at LCCOMB_X42_Y34_N18
cycloneii_lcell_comb \counter[3]~96_I (
// Equation(s):
// \counter[3]~96  = \counter[3]~reg0  & !\counter[2]~95  # !\counter[3]~reg0  & (\counter[2]~95  # GND)
// \counter[3]~97  = CARRY(!\counter[2]~95  # !\counter[3]~reg0 )

	.dataa(vcc),
	.datab(\counter[3]~reg0 ),
	.datac(vcc),
	.datad(vcc),
	.cin(\counter[2]~95 ),
	.combout(\counter[3]~96 ),
	.cout(\counter[3]~97 ));
// synopsys translate_off
defparam \counter[3]~96_I .sum_lutc_input = "cin";
defparam \counter[3]~96_I .lut_mask = 16'h3C3F;
// synopsys translate_on

// atom is at LCFF_X42_Y34_N19
cycloneii_lcell_ff \counter[3]~reg0_I (
	.clk(\sys_clk~clkctrl ),
	.datain(\counter[3]~96 ),
	.sdata(),
	.aclr(!\rst_n~clkctrl ),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(\counter[3]~reg0 ));

// atom is at LCCOMB_X42_Y34_N20
cycloneii_lcell_comb \counter[4]~98_I (
// Equation(s):
// \counter[4]~98  = \counter[4]~reg0  & (\counter[3]~97  $ GND) # !\counter[4]~reg0  & !\counter[3]~97  & VCC
// \counter[4]~99  = CARRY(\counter[4]~reg0  & !\counter[3]~97 )

	.dataa(\counter[4]~reg0 ),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.cin(\counter[3]~97 ),
	.combout(\counter[4]~98 ),
	.cout(\counter[4]~99 ));
// synopsys translate_off
defparam \counter[4]~98_I .sum_lutc_input = "cin";
defparam \counter[4]~98_I .lut_mask = 16'hA50A;
// synopsys translate_on

// atom is at LCFF_X42_Y34_N21
cycloneii_lcell_ff \counter[4]~reg0_I (
	.clk(\sys_clk~clkctrl ),
	.datain(\counter[4]~98 ),
	.sdata(),
	.aclr(!\rst_n~clkctrl ),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(\counter[4]~reg0 ));

// atom is at LCCOMB_X42_Y34_N22
cycloneii_lcell_comb \counter[5]~100_I (
// Equation(s):
// \counter[5]~100  = \counter[5]~reg0  & !\counter[4]~99  # !\counter[5]~reg0  & (\counter[4]~99  # GND)
// \counter[5]~101  = CARRY(!\counter[4]~99  # !\counter[5]~reg0 )

	.dataa(vcc),
	.datab(\counter[5]~reg0 ),
	.datac(vcc),
	.datad(vcc),
	.cin(\counter[4]~99 ),
	.combout(\counter[5]~100 ),
	.cout(\counter[5]~101 ));
// synopsys translate_off
defparam \counter[5]~100_I .sum_lutc_input = "cin";
defparam \counter[5]~100_I .lut_mask = 16'h3C3F;
// synopsys translate_on

// atom is at LCFF_X42_Y34_N23
cycloneii_lcell_ff \counter[5]~reg0_I (
	.clk(\sys_clk~clkctrl ),
	.datain(\counter[5]~100 ),
	.sdata(),
	.aclr(!\rst_n~clkctrl ),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(\counter[5]~reg0 ));

// atom is at LCCOMB_X42_Y34_N24
cycloneii_lcell_comb \counter[6]~102_I (
// Equation(s):
// \counter[6]~102  = \counter[6]~reg0  & (\counter[5]~101  $ GND) # !\counter[6]~reg0  & !\counter[5]~101  & VCC
// \counter[6]~103  = CARRY(\counter[6]~reg0  & !\counter[5]~101 )

	.dataa(\counter[6]~reg0 ),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.cin(\counter[5]~101 ),
	.combout(\counter[6]~102 ),
	.cout(\counter[6]~103 ));
// synopsys translate_off
defparam \counter[6]~102_I .sum_lutc_input = "cin";
defparam \counter[6]~102_I .lut_mask = 16'hA50A;
// synopsys translate_on

// atom is at LCFF_X42_Y34_N25
cycloneii_lcell_ff \counter[6]~reg0_I (
	.clk(\sys_clk~clkctrl ),
	.datain(\counter[6]~102 ),
	.sdata(),
	.aclr(!\rst_n~clkctrl ),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(\counter[6]~reg0 ));

// atom is at LCCOMB_X42_Y34_N26
cycloneii_lcell_comb \counter[7]~104_I (
// Equation(s):
// \counter[7]~104  = \counter[7]~reg0  & !\counter[6]~103  # !\counter[7]~reg0  & (\counter[6]~103  # GND)
// \counter[7]~105  = CARRY(!\counter[6]~103  # !\counter[7]~reg0 )

	.dataa(vcc),
	.datab(\counter[7]~reg0 ),
	.datac(vcc),
	.datad(vcc),
	.cin(\counter[6]~103 ),
	.combout(\counter[7]~104 ),
	.cout(\counter[7]~105 ));
// synopsys translate_off
defparam \counter[7]~104_I .sum_lutc_input = "cin";
defparam \counter[7]~104_I .lut_mask = 16'h3C3F;
// synopsys translate_on

// atom is at LCFF_X42_Y34_N27
cycloneii_lcell_ff \counter[7]~reg0_I (
	.clk(\sys_clk~clkctrl ),
	.datain(\counter[7]~104 ),
	.sdata(),
	.aclr(!\rst_n~clkctrl ),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(\counter[7]~reg0 ));

// atom is at LCCOMB_X42_Y34_N28
cycloneii_lcell_comb \counter[8]~106_I (
// Equation(s):
// \counter[8]~106  = \counter[8]~reg0  & (\counter[7]~105  $ GND) # !\counter[8]~reg0  & !\counter[7]~105  & VCC
// \counter[8]~107  = CARRY(\counter[8]~reg0  & !\counter[7]~105 )

	.dataa(vcc),
	.datab(\counter[8]~reg0 ),
	.datac(vcc),
	.datad(vcc),
	.cin(\counter[7]~105 ),
	.combout(\counter[8]~106 ),
	.cout(\counter[8]~107 ));
// synopsys translate_off
defparam \counter[8]~106_I .sum_lutc_input = "cin";
defparam \counter[8]~106_I .lut_mask = 16'hC30C;
// synopsys translate_on

// atom is at LCFF_X42_Y34_N29
cycloneii_lcell_ff \counter[8]~reg0_I (
	.clk(\sys_clk~clkctrl ),
	.datain(\counter[8]~106 ),
	.sdata(),
	.aclr(!\rst_n~clkctrl ),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(\counter[8]~reg0 ));

// atom is at LCCOMB_X42_Y34_N30
cycloneii_lcell_comb \counter[9]~108_I (
// Equation(s):
// \counter[9]~108  = \counter[8]~107  $ \counter[9]~reg0 

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\counter[9]~reg0 ),
	.cin(\counter[8]~107 ),
	.combout(\counter[9]~108 ),
	.cout());
// synopsys translate_off
defparam \counter[9]~108_I .sum_lutc_input = "cin";
defparam \counter[9]~108_I .lut_mask = 16'h0FF0;
// synopsys translate_on

// atom is at LCFF_X42_Y34_N31
cycloneii_lcell_ff \counter[9]~reg0_I (
	.clk(\sys_clk~clkctrl ),
	.datain(\counter[9]~108 ),
	.sdata(),
	.aclr(!\rst_n~clkctrl ),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(\counter[9]~reg0 ));

// atom is at M4K_X43_Y35
cycloneii_ram_block \sintab1|altsyncram_component|auto_generated|ram_block1a0 (
	.portawe(gnd),
	.portaaddrstall(gnd),
	.portbrewe(vcc),
	.portbaddrstall(gnd),
	.clk0(\sys_clk~clkctrl ),
	.clk1(gnd),
	.ena0(vcc),
	.ena1(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND ,\~GND ,\~GND ,\~GND }),
	.portaaddr({\counter[9]~reg0 ,\counter[8]~reg0 ,\counter[7]~reg0 ,\counter[6]~reg0 ,\counter[5]~reg0 ,\counter[4]~reg0 ,\counter[3]~reg0 ,\counter[2]~reg0 ,\counter[1]~reg0 ,\counter[0]~reg0 }),
	.portabyteenamasks(),
	.portbdatain(),
	.portbaddr(),
	.portbbyteenamasks(),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\sintab1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M4K";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|ALTSYNCRAM";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "sintab.mif";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 1024;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 14;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_in_clear = "none";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clear = "none";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clear = "none";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 1023;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 4;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 10;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 10;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 4;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a0 .safe_write = "err_on_2clk";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'hFFDCCAA8997755533111FFDDCABB9877654323010EFDCCABB9866754432100FFECCCAA898676554223100FFEDCDBAA8897665542331001FFEDDDBBBA989766755432221001FEEFDDDCABBA88887676644552233310101FFFFEFCCCCCBABAAAA989988976677774544444545333232333323000001011110100000101111010000010111101000001011110100000323333232333545444445477776679889989AAAABABCCCCCFEFFFF10101333225544667678888ABBACDDDFEEF100022234557667989ABBBDDDEFE1001332455667988AABDCDEFF001322455676898AACCCEFF0012344576689BBACCDFE0103234567789BBACDDFF1113355577998AACCDFF0;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h002335576688AAACCEEE0022354467889ABCDCFEF1023354467998ABBCDEFF00133355767989AABDDCEFF001232455776899AABDCCEFFE10122244456768998AABCDDDEFFE011022235445777789899BBAADDCCCEFEFE00001033333454555567667768998888BABBBBBABACCCDCDCCCCDCFFFFFEFEEEEFEFFFFFEFEEEEFEFFFFFEFEEEEFEFFFFFEFEEEEFEFFFFFCDCCCCDCDCCCABABBBBBAB88889986776676555545433333010000EFEFECCCDDAABB998987777544532220110EFFEDDDCBAA89986765444222101EFFECCDBAA998677554232100FFECDDBAA98976755333100FFEDCBBA8997644533201FEFCDCBA9887644532200EEECCAAA886675533200F;
// synopsys translate_on

// atom is at M4K_X43_Y33
cycloneii_ram_block \sintab1|altsyncram_component|auto_generated|ram_block1a1 (
	.portawe(gnd),
	.portaaddrstall(gnd),
	.portbrewe(vcc),
	.portbaddrstall(gnd),
	.clk0(\sys_clk~clkctrl ),
	.clk1(gnd),
	.ena0(vcc),
	.ena1(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.portadatain({\~GND ,\~GND ,\~GND ,\~GND }),
	.portaaddr({\counter[9]~reg0 ,\counter[8]~reg0 ,\counter[7]~reg0 ,\counter[6]~reg0 ,\counter[5]~reg0 ,\counter[4]~reg0 ,\counter[3]~reg0 ,\counter[2]~reg0 ,\counter[1]~reg0 ,\counter[0]~reg0 }),
	.portabyteenamasks(),
	.portbdatain(),
	.portbaddr(),
	.portbbyteenamasks(),
	.devclrn(devclrn),
	.devpor(devpor),
	.portadataout(\sintab1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ),
	.portbdataout());
// synopsys translate_off
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M4K";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated|ALTSYNCRAM";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "sintab.mif";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 1024;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 14;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_in_clear = "none";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clear = "none";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clear = "none";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 1023;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 0;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 4;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 10;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 10;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 4;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a1 .safe_write = "err_on_2clk";
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h45674567745674547654323003210230013201320477557644775576447745301230123023003113302317746756747656656446557464030230303102131311302121312164657574647474747564464647447475465311300303212213311300321031122003321032110220112230110222200112322331111100101100000001101001111133223211002222011032211022011230123300221130123003113312212303003113564574744746464465747474746475756461212121203113131201303032031464755644656656747657647713203311300320321032103547744675577446755774023102310032012300323456745476547765476548;
defparam \sintab1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hBA98BA988BA98BAB89ABCDCFFCDEFDCFFECDFECDFB88AA89BB88AA89BB88BACFEDCFEDCFDCFFCEECCFDCE88B98A98B89A99A9BB9AA8B9BECFDCFCFCEFDECECEECFDEDECEDE9B9A8A8B9B8B8B8B8A9BB9B9B8BB8B8AB9ACEECFFCFCDEDDECCEECFFCDEFCEEDDFFCCDEFCDEEFDDFEEDDCFEEFDDDDFFEEDCDDCCEEEEEFFEFEEFFFFFFFEEFEFFEEEEECCDDCDEEFFDDDDFEEFCDDEEFDDFEEDCFEDCCFFDDEECFEDCFFCEECCEDDEDCFCFFCEECA9BA8B8BB8B9B9BB9A8B8B8B8B9B8A8A9B9EDECEDEDFCEECECEDFECFCFCDFCEB9B8AA9BB9A99A98B89A89B88ECDFCCEECFFCDFCDEFCDEFCAB88BB98AA88BB98AA88BFDCEFDCEFFCDFEDCFFCDCBA98BAB89AB889AB89AB7;
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