changing_epp.v

verilog语言编写的FPGA代码。功能为pc机通过epp不断写数到sram中

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    15:43:45 04/24/07
// Design Name:    
// Module Name:    epp
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module changing_epp(EPP_Write0,EPP_Data,EPP_Interrupt,EPP_Wait,EPP_DataStrobe0,EPP_Reset0,
	EPP_AddressStrobe0 , write , waddr , raddr , din , dout , sys_clock ,
	// , rst 
	//,x_read , finished_cal
	x,y,needread
	);

//	input rst;
	input sys_clock;


	//EPP interface signals
	input EPP_Write0;
	inout [7:0] EPP_Data;
	
	input EPP_DataStrobe0;
	input EPP_Reset0;
	input EPP_AddressStrobe0;

	output EPP_Interrupt;
	output EPP_Wait;
  /*
	input x_read;
	input finished_cal;
	reg x_read0;
	reg finished_cal0;
*/	
	output write ;
	output [19:0] waddr;	
	output [19:0] raddr;	
	output [7:0] din;	 //sram输入		
	input [7:0] dout;	 //sram输出

	input [15:0] x;
	input [15:0] y;
	reg [15:0] x_in;
	reg [15:0] y_in;	

	reg [19:0] waddr;
	reg [19:0] raddr;
//	reg [7:0] din;

	reg [7:0] dout0;
/******************** module regs define ***********************************/

	//regs related to EPP
	reg EPP_Interrupt,EPP_Wait;
	reg EPP_Write,EPP_DataStrobe,EPP_AddressStrobe,EPP_Reset;
	reg temp_reset;
	reg [7:0] epp_dataout;

	//中间寄存器

	reg [2:0] epp_state;
//	reg [7:0] cmd;//from epp address write
	reg [2:0] cmd_state;
	
	input needread;
	reg needread0;

	//regs for test
//   reg epp_clock;

// regs for initialize ram
	reg write;//低电平时为写,初始化SRAM,高电平时为读

	reg [1:0] rst_counter;
	reg [10:0] counter;
	parameter COUNT=100;

	reg [7:0] dataout;

/**********************  module constant define  *******************************/
	//parameters EPP state
	parameter EPP_IDLE=3'b000,EPP_WAIT_ADDRREAD=3'b001,EPP_WAIT_ADDRWRITE=3'b010,
		EPP_WAIT_DATAREAD=3'b011,EPP_WAIT_DATAWRITE=3'b100;

	parameter CMD_IDLE=3'b000,CMD_WAIT_EOS_FRAME=3'b001,CMD_PC_READ=3'b010,CMD_WAIT_EOS_CAL=3'b100;

always @ (posedge sys_clock)
begin
	if (!EPP_Reset)
		dout0 <= 0;
	else
		dout0 <= dout;
end

always @ (posedge sys_clock)
begin
	if (!EPP_Reset)
		needread0 <= 0;
	else
		needread0 <= needread ;
end

/*
always @ (posedge sys_clock)
begin
	if (!rst)
		x_read0 <= 0;
	else
		x_read0 <= x_read ;
end

always @ (posedge sys_clock)
begin
	if (!rst)
		finished_cal0 <= 0;
	else
		finished_cal0 <= finished_cal;
end
			  */

assign din=waddr;

always @ (posedge sys_clock)
begin
	if(!EPP_Reset)
	begin
		write<=0;
		cmd_state<=CMD_IDLE;
		EPP_Interrupt<=0;
		counter<=COUNT;
	//	din<=0;
		waddr<=0;
	end
	else
		case(cmd_state)
			CMD_IDLE:
			begin
				write<=0;   //选中写信号,PC不读的话FPGA一直写入SRAM
				cmd_state<=CMD_IDLE;
				EPP_Interrupt<=0;
				if(!needread0) //PC不需要读则给IBIS4读信号，写入SRAM
				begin
					write<=0; //选中SRAM写信号
					cmd_state<=CMD_WAIT_EOS_CAL;//CMD_WAIT_EOS_FRAME;
				end
				else
				begin
					write<=1; //开始读信号	  !!!!!
					EPP_Interrupt<=1; //给PC可读信号	 !!!!!!!
					cmd_state<=CMD_PC_READ;
				end
			end
		
			CMD_WAIT_EOS_CAL: //等待计算质心
			begin
			/*	if(x_read0)
				begin
					waddr<=waddr+1;
				end*/
				
				cmd_state<=CMD_WAIT_EOS_CAL;
				counter<=counter-1;
				waddr<=waddr+1;
				if(counter[10])		//模拟计算过程,应为计算后往SRAM中写数
				begin			//这样写是模拟一直在写数.
					counter<=COUNT;
					waddr<=0;
				//	waddr<=waddr+1;
				//	din<=waddr;
					x_in<=x;
					y_in<=y;
					cmd_state<=CMD_IDLE;
				end
			end

			CMD_PC_READ:
			begin
				cmd_state<=CMD_PC_READ;
				if(!needread0)  //PC清除了读信号
				begin
					write<=0;
					EPP_Interrupt<=0;			 //PC不可读!!!!!!!
					cmd_state<=CMD_IDLE;
				end
			end
			default:
				cmd_state<=CMD_IDLE;
		endcase		
end


/*********************  module internal logic  *********************************/

//并口输入进来的信号，需要同步。加入锁存器
always @ (posedge sys_clock)
begin
		temp_reset<=EPP_Reset0;
		EPP_Reset<=temp_reset;
end

always @ (posedge sys_clock)
begin
	if(!EPP_Reset)
		EPP_Write<=1;
	else
		EPP_Write<=EPP_Write0;
end

always @ (posedge sys_clock)
begin
	if(!EPP_Reset)
		EPP_DataStrobe<=1;
	else
		EPP_DataStrobe<=EPP_DataStrobe0;
end

always @ (posedge sys_clock)
begin
	if(!EPP_Reset)
		EPP_AddressStrobe<=1;
	else
		EPP_AddressStrobe<=EPP_AddressStrobe0;
end

/*
always @ (posedge sys_clock)
begin
	if(!EPP_Reset)
		epp_clock<=0;
	else
		epp_clock<=~epp_clock;
end
*/


//EPP state machine
always @ (posedge sys_clock)
begin
	if(!EPP_Reset )
	begin
		epp_state<=EPP_IDLE;
		EPP_Wait<=0;
		epp_dataout<=8'b0;
		raddr<=0;
		rst_counter<=0;
		dataout<=0;//addition
	end
	else
		case(epp_state)
			EPP_IDLE:
			begin															 
				epp_state<=EPP_IDLE;
				EPP_Wait<=0;
				if(!EPP_AddressStrobe)//&&epp_clock)  
				begin
					if(EPP_Write)	//EPP_Write==1,EPP_AddressStrobe==0
					begin//EPP address read
					//	epp_dataout<=write?raddr:waddr;
					//	needread<=~EPP_Data[0]; //为什么不加？

						case(rst_counter)
							0:epp_dataout<=x_in[15:8];//以后应该加上小数位,传输最终结果
							1:epp_dataout<=x_in[7:0];//为什么传输最终结果的时候会传2次?
							2:epp_dataout<=y_in[15:8];
							3:epp_dataout<=y_in[7:0];
						endcase
							
						rst_counter<=rst_counter+1;

						EPP_Wait<=1;
						epp_state<=EPP_WAIT_ADDRREAD;
					end
					else	//EPP_Write==0,EPP_AddressStrobe==0
					begin//EPP address write    cmd come from EPP address write
					//	needread <= EPP_Data[0];//neadread低电平为写有效,与write相同
					//	needread<=0;
						EPP_Wait<=1;
						epp_state<=EPP_WAIT_ADDRWRITE;
					end
				end
				else if(!EPP_DataStrobe)//&&epp_clock)
				begin
					if(EPP_Write)	//EPP_Write==1,EPP_DataStrobe==0
					begin//EPP data read
					//	epp_dataout<=dout0;//从sram中读到的数据输出给epp端口
						epp_dataout<=dataout;//测试随便一个数
						dataout<=dataout+1;
						EPP_Wait<=1;
						epp_state<=EPP_WAIT_DATAREAD;
					end
					else	//EPP_Write==0,EPP_DataStrobe==0
					begin//EPP data write
					//	din<=EPP_Data;	//从epp端口独到的数据输入给sram,FPGA写入SRAM时注释掉
					//	din<=counter;	//测试用,写一个counter
						EPP_Wait<=1;
						epp_state<=EPP_WAIT_DATAWRITE;
					end
				end
			end
			EPP_WAIT_ADDRREAD:
			begin
				if(EPP_AddressStrobe)//&&epp_clock)
				begin
					EPP_Wait<=0;
					epp_state<=EPP_IDLE;
				end
			end
			EPP_WAIT_ADDRWRITE:
			begin
				if(EPP_AddressStrobe)//&&epp_clock)
				begin
					EPP_Wait<=0;
					epp_state<=EPP_IDLE;
				end
			end
			EPP_WAIT_DATAREAD:
			begin
				if(EPP_DataStrobe)//&&epp_clock)
				begin
					EPP_Wait<=0;
					epp_state<=EPP_IDLE;
					raddr<=raddr+1;
				end
			end
			EPP_WAIT_DATAWRITE:
			begin
				if(EPP_DataStrobe)//&&epp_clock)
				begin
					EPP_Wait<=0;
					epp_state<=EPP_IDLE;
				//	waddr<=waddr+1;
				end
			end
			default: epp_state<=EPP_IDLE;
		endcase
	end

  assign EPP_Data=((epp_state==EPP_WAIT_DATAREAD)||(epp_state==EPP_WAIT_ADDRREAD))?epp_dataout:8'bz;


endmodule