epp_sram.v

verilog语言编写的FPGA代码。功能为pc机通过epp不断写数到sram中

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    21:11:13 04/26/07
// Design Name:    
// Module Name:    epp_sram
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module epp_sram(
	//sram
	sram_ce,sram_oe,sram_we,sram_io,sram_addr,sys_clock,
	//rst,
	waddr,raddr,din,dout,write,
	//epp
	EPP_Write0,EPP_Data,EPP_Interrupt,EPP_Wait,EPP_DataStrobe0,EPP_Reset0,
	EPP_AddressStrobe0, 
	//,finished_cal, x_read
	x,y,needread
);
	
	output sram_ce;
	output sram_oe;
	output sram_we;
	inout  [7:0] sram_io;
	output [19:0] sram_addr;

	//signals from or to internal logic
	input sys_clock;
//	input rst;

	output [19:0] waddr;   //从IBIS4 xmodule来，写SRAM的地址		//wire
	output [19:0] raddr;	//从控制逻辑来，EPP						  //wire

	output write;  //内部逻辑输入，低表示写，高读SRAM			  //wire
	output [7:0] din;	//从IBIS4 xmodule来，写入SRAM的data		  //wire
	output [7:0] dout;	//把SRAM的数输出到并口					 //wire

//	input x_read;
//	input finished_cal;


	input EPP_Write0;
	inout [7:0] EPP_Data;
	output EPP_Interrupt;
	output EPP_Wait;
	input EPP_DataStrobe0;
	input EPP_Reset0;
	input EPP_AddressStrobe0;
	
	input [15:0] x;
	input [15:0] y;
	input needread;

	sram sram(.sram_ce(sram_ce) , .sram_oe(sram_oe) , .sram_we(sram_we) , .sram_io(sram_io) , 
	.sram_addr(sram_addr) , .sys_clock(sys_clock) , .EPP_Reset0(EPP_Reset0) , .waddr(waddr) , 
		.raddr(raddr) , .din(din) , .dout(dout) , .write(write) );

	changing_epp changing_epp( .EPP_Write0(EPP_Write0) , .EPP_Data(EPP_Data) , .EPP_Interrupt(EPP_Interrupt) ,
	.EPP_Wait(EPP_Wait) , .EPP_DataStrobe0(EPP_DataStrobe0) , .EPP_Reset0(EPP_Reset0) , 
	.EPP_AddressStrobe0(EPP_AddressStrobe0) , 
	.write(write) , .waddr(waddr) , .raddr(raddr) , .din(din) ,	.dout(dout) ,
	.sys_clock(sys_clock) 
	//, .rst(rst) 
//	, .x_read(x_read) , .finished_cal(finished_cal)
	, .x(x) , .y(y) , .needread(needread)
	);

endmodule