test_changing.v

verilog语言编写的FPGA代码。功能为pc机通过epp不断写数到sram中

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   17:00:37 06/20/2007
// Design Name:   epp_sram
// Module Name:   test_changing.v
// Project Name:  Cmd_EPP
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: epp_sram
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module test_changing_v;

	// Inputs
	reg sys_clock;
	reg EPP_Write0;
	reg EPP_DataStrobe0;
	reg EPP_Reset0;
	reg EPP_AddressStrobe0;
	reg [15:0] x;
	reg [15:0] y;
	reg needread;

	// Outputs
	wire sram_ce;
	wire sram_oe;
	wire sram_we;
	wire [19:0] sram_addr;
	wire EPP_Interrupt;
	wire EPP_Wait;

	wire [19:0] waddr,raddr;
	wire [7:0] din,dout;
	wire write;//wire

	// Bidirs
	wire [7:0] sram_io;
	wire [7:0] EPP_Data;

	reg [10:0] counter;
	parameter COUNT=10;
	
	parameter EPP_IDLE=3'b000,EPP_WAIT_ADDRREAD=3'b001,EPP_WAIT_ADDRWRITE=3'b010,
		EPP_WAIT_DATAREAD=3'b011,EPP_WAIT_DATAWRITE=3'b100;
	// Instantiate the Unit Under Test (UUT)
	epp_sram uut (
		.sram_ce(sram_ce), 
		.sram_oe(sram_oe), 
		.sram_we(sram_we), 
		.sram_io(sram_io), 
		.sram_addr(sram_addr), 
		.sys_clock(sys_clock),
		.waddr(waddr),
		.raddr(raddr),
		.din(din),
		.dout(dout),
		.write(write),
		.EPP_Write0(EPP_Write0), 
		.EPP_Data(EPP_Data), 
		.EPP_Interrupt(EPP_Interrupt), 
		.EPP_Wait(EPP_Wait), 
		.EPP_DataStrobe0(EPP_DataStrobe0), 
		.EPP_Reset0(EPP_Reset0), 
		.EPP_AddressStrobe0(EPP_AddressStrobe0), 
		.x(x), 
		.y(y), 
		.needread(needread)
	);

	always #10 sys_clock = ~sys_clock;

	always @ (posedge sys_clock)
	begin
		if(needread)
		begin
			counter = counter - 1;
			if (counter[10])
			begin
				EPP_DataStrobe0 = ~EPP_DataStrobe0;
				EPP_AddressStrobe0 = ~EPP_AddressStrobe0;
				counter = COUNT;
			end
		end
/*		else
		begin
			EPP_DataStrobe0 = 1;
			EPP_AddressStrobe0 = 0;
		end*/
		
	end
	

	initial begin
		// Initialize Inputs
		sys_clock = 0;
		EPP_Write0 = 1;
		EPP_DataStrobe0 = 1;
		EPP_Reset0 = 0;
		EPP_AddressStrobe0 = 1;
		x = 2000;
		y = 2300;
		needread = 0;
		counter = COUNT;

		// Wait 100 ns for global reset to finish
		#100;
       		EPP_Reset0 = 1;
		#1000	needread = 1;
		#20	EPP_AddressStrobe0 = 0;
	//	#100 	EPP_AddressStrobe0 = 0;
	//	#1000 	EPP_AddressStrobe0 = 1;
	//	#100 	EPP_AddressStrobe0 = 1;
		#10000	needread = 0;
		
//		#500	needread = 1;
//		#1000	needread = 0;
		// Add stimulus here
		#3000 $stop;

	end

endmodule