sram.v

verilog语言编写的FPGA代码。功能为pc机通过epp不断写数到sram中

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    15:43:37 04/24/07
// Design Name:    
// Module Name:    sram
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module sram(sram_ce,sram_oe,sram_we,sram_io,sram_addr,sys_clock,
	EPP_Reset0,waddr,raddr,din,dout,write);
/************************ module ports define ********************************/
	
	

	//signals from or to internal logic
	input sys_clock;
	input EPP_Reset0;

	reg EPP_Reset,temp_reset;

	input [19:0] waddr;   //从IBIS4 xmodule来，写SRAM的地址
	input [19:0] raddr;	//从控制逻辑来，EPP
	input write;  //内部逻辑输入，低表示写，高读SRAM
	input [7:0] din;	//从IBIS4 xmodule来，写入SRAM的data
	
	output [7:0] dout;	//把SRAM的数输出到并口

	//signals from or to sram chip
	output sram_ce;
	output sram_oe;
	output sram_we;
	inout  [7:0] sram_io;
	output [19:0] sram_addr;
/************************* module reg and wire define ***********************/
	reg sram_ce;
/************************ module logic define ******************************/
assign sram_oe=~write;
assign sram_we=write;
assign sram_addr=(write)?raddr:waddr;

assign sram_io=(write)?8'bz:din;
//assign sram_io=(write)?dout:din;

//assign dout=(write)?sram_io:8'bz;
assign dout=sram_io;


always @ (negedge sys_clock)
begin
	temp_reset <= EPP_Reset0;
	EPP_Reset <= temp_reset;
end

always @ (negedge sys_clock)
	if(!EPP_Reset)
		sram_ce<=1;
	else
		sram_ce<=0;  //一直选中SRAM	


endmodule