fir_da.v

完成一个FIR数字滤波器的设计。要求： 1、 基于直接型和分布式两种算法。 2、 输入数据宽度为8位

//-----------------------
//  module description
//-----------------------
  module fir_da(
		            //input
		            din,
		            clock,
		            reset,
		            //
		            dout
		             );
             
//-----------------------
//  port declaration
//-----------------------
  input  [7:0]  din;
  input         clock;
  input         reset;
  
  output [15:0] dout;
  
//-----------------------------------------------------
//  signal declaration
//-----------------------------------------------------
  reg [7:0] din_reg_00_8b;  //移位寄存器
  reg [7:0] din_reg_01_8b;
  reg [7:0] din_reg_02_8b;
  reg [7:0] din_reg_03_8b;
  reg [7:0] din_reg_04_8b;
  reg [7:0] din_reg_05_8b;
  reg [7:0] din_reg_06_8b;
  reg [7:0] din_reg_07_8b;
  reg [7:0] din_reg_08_8b;
  reg [7:0] din_reg_09_8b;      
  reg [7:0] din_reg_10_8b;
  reg [7:0] din_reg_11_8b;
  reg [7:0] din_reg_12_8b;
  reg [7:0] din_reg_13_8b;
  reg [7:0] din_reg_14_8b;
  
	function[15:0] lookuplow;
	  input [3:0] din;
	  begin
	  	case(din)
			   4'b0000: lookuplow=16'h0;
			   4'b0001: lookuplow=16'h0;
			   4'b0010: lookuplow=16'h65;
			   4'b0011: lookuplow=16'h65;
			   4'b0100: lookuplow=16'h18f;
			   4'b0101: lookuplow=16'h18f;
			   4'b0110: lookuplow=16'h1f4;
			   4'b0111: lookuplow=16'h1f4;
			   4'b1000: lookuplow=16'h35a;
			   4'b1001: lookuplow=16'h35a;
			   4'b1010: lookuplow=16'h3bf;
			   4'b1011: lookuplow=16'h3bf;
			   4'b1100: lookuplow=16'h4e9;
			   4'b1101: lookuplow=16'h4e9;
			   4'b1110: lookuplow=16'h54e;
			   4'b1111: lookuplow=16'h54e;
			endcase
		end
	endfunction
	  	  
	
	function[15:0] lookuphigh;
	  input [3:0] din;
	  begin
	  	case(din) 
			   4'b0000: lookuphigh=16'h0;
			   4'b0001: lookuphigh=16'h579;
			   4'b0010: lookuphigh=16'h78e;
			   4'b0011: lookuphigh=16'hd07;
			   4'b0100: lookuphigh=16'h935;
			   4'b0101: lookuphigh=16'heae;
			   4'b0110: lookuphigh=16'h10c3;
			   4'b0111: lookuphigh=16'h163c;
			   4'b1000: lookuphigh=16'h0a1f;
			   4'b1001: lookuphigh=16'h0f98;
			   4'b1010: lookuphigh=16'h11ad;
			   4'b1011: lookuphigh=16'h1726;
			   4'b1100: lookuphigh=16'h1354;
			   4'b1101: lookuphigh=16'h18cd;
			   4'b1110: lookuphigh=16'h1ae2;
			   4'b1111: lookuphigh=16'h205b;
			endcase
		end
	endfunction 
	

//------------------------------------------------
//  移位寄存器单元
//------------------------------------------------
           
  always @(posedge clock or posedge reset )
      if (reset==1)
          begin
              din_reg_00_8b <= 8'b0;
              din_reg_01_8b <= 8'b0;
              din_reg_02_8b <= 8'b0;
              din_reg_03_8b <= 8'b0;
              din_reg_04_8b <= 8'b0;
              din_reg_05_8b <= 8'b0;
              din_reg_06_8b <= 8'b0;
              din_reg_07_8b <= 8'b0;
              din_reg_08_8b <= 8'b0;
              din_reg_09_8b <= 8'b0;
              din_reg_10_8b <= 8'b0;
              din_reg_11_8b <= 8'b0;
              din_reg_12_8b <= 8'b0;
              din_reg_13_8b <= 8'b0;
              din_reg_14_8b <= 8'b0;
          end
      else
          begin
              din_reg_00_8b <= din;
              din_reg_01_8b <= din_reg_00_8b;
              din_reg_02_8b <= din_reg_01_8b;
              din_reg_03_8b <= din_reg_02_8b;
              din_reg_04_8b <= din_reg_03_8b;
              din_reg_05_8b <= din_reg_04_8b;
              din_reg_06_8b <= din_reg_05_8b;
              din_reg_07_8b <= din_reg_06_8b;
              din_reg_08_8b <= din_reg_07_8b;
              din_reg_09_8b <= din_reg_08_8b;
              din_reg_10_8b <= din_reg_09_8b;
              din_reg_11_8b <= din_reg_10_8b;
              din_reg_12_8b <= din_reg_11_8b;
              din_reg_13_8b <= din_reg_12_8b;
              din_reg_14_8b <= din_reg_13_8b;
          end
          
//------------------------------------------------
//  查找表单元
//------------------------------------------------
  reg [16:0] lookup0_1_1,lookup0_1_2,lookup0_1_3,lookup0_1_4,
             lookup1_1_1,lookup1_1_2,lookup1_1_3,lookup1_1_4,
             lookup2_1_1,lookup2_1_2,lookup2_1_3,lookup2_1_4,
             lookup3_1_1,lookup3_1_2,lookup3_1_3,lookup3_1_4,
             lookup4_1_1,lookup4_1_2,lookup4_1_3,lookup4_1_4,
             lookup5_1_1,lookup5_1_2,lookup5_1_3,lookup5_1_4,
             lookup6_1_1,lookup6_1_2,lookup6_1_3,lookup6_1_4,
             lookup7_1_1,lookup7_1_2,lookup7_1_3,lookup7_1_4;
  reg [17:0] lookup1_2_1,lookup1_2_2,lookup0_2_1,lookup0_2_2,
             lookup3_2_1,lookup3_2_2,lookup2_2_1,lookup2_2_2,
             lookup5_2_1,lookup5_2_2,lookup4_2_1,lookup4_2_2,
             lookup7_2_1,lookup7_2_2,lookup6_2_1,lookup6_2_2;
  reg [18:0] lookup0,lookup1,lookup2,lookup3,lookup4,lookup5,lookup6,lookup7;
            
  
  always @(posedge clock or posedge reset)
      if (reset)
          begin
            lookup0_1_1 <= 0;
            lookup0_1_2 <= 0;
            lookup0_1_3 <= 0;
            lookup0_1_4 <= 0;
            lookup0_2_1 <= 0;
            lookup0_2_2 <= 0;
            lookup0     <= 0;
            lookup1_1_1 <= 0;
            lookup1_1_2 <= 0;
            lookup1_1_3 <= 0;
            lookup1_1_4 <= 0;
            lookup1_2_1 <= 0;
            lookup1_2_2 <= 0;
            lookup1     <= 0;
            lookup2_1_1 <= 0;
            lookup2_1_2 <= 0;
            lookup2_1_3 <= 0;
            lookup2_1_4 <= 0;
            lookup2_2_1 <= 0;
            lookup2_2_2 <= 0;
            lookup2     <= 0;
            lookup3_1_1 <= 0;
            lookup3_1_2 <= 0;
            lookup3_1_3 <= 0;
            lookup3_1_4 <= 0;
            lookup3_2_1 <= 0;
            lookup3_2_2 <= 0;