fir.v

完成一个FIR数字滤波器的设计。要求： 1、 基于直接型和分布式两种算法。 2、 输入数据宽度为8位

//-----------------------
//  module description
//-----------------------
  module fir(
             //input
             din,
             clock,
             reset,
             //
             dout
             );
             
//-----------------------
//  port declaration
//-----------------------
  input  [7:0]  din;
  input         clock;
  input         reset;
  
  output [16:0] dout;
  
//-----------------------------------------------------
//  signal declaration
//-----------------------------------------------------
  reg [7:0] din_reg_00_8b;  //移位寄存器
  reg [7:0] din_reg_01_8b;
  reg [7:0] din_reg_02_8b;
  reg [7:0] din_reg_03_8b;
  reg [7:0] din_reg_04_8b;
  reg [7:0] din_reg_05_8b;
  reg [7:0] din_reg_06_8b;
  reg [7:0] din_reg_07_8b;
  reg [7:0] din_reg_08_8b;
  reg [7:0] din_reg_09_8b;      
  reg [7:0] din_reg_10_8b;
  reg [7:0] din_reg_11_8b;
  reg [7:0] din_reg_12_8b;
  reg [7:0] din_reg_13_8b;
  reg [7:0] din_reg_14_8b;
  
  reg [8:0] sum_0_9b;   //预相加结果
  reg [8:0] sum_1_9b;
  reg [8:0] sum_2_9b;
  reg [8:0] sum_3_9b;
  reg [8:0] sum_4_9b;
  reg [8:0] sum_5_9b;
  reg [8:0] sum_6_9b;
  reg [8:0] sum_7_9b;
  
  wire [24:0] mult_0_25b;  //乘法结果
  wire [24:0] mult_1_25b;
  wire [24:0] mult_2_25b;
  wire [24:0] mult_3_25b;
  wire [24:0] mult_4_25b;
  wire [24:0] mult_5_25b;
  wire [24:0] mult_6_25b;
  wire [24:0] mult_7_25b;
  
  reg  [27:0] mult_0_28b;  //乘法结果
  reg  [27:0] mult_1_28b;
  reg  [27:0] mult_2_28b;
  reg  [27:0] mult_3_28b;
  reg  [27:0] mult_4_28b;
  reg  [27:0] mult_5_28b;
  reg  [27:0] mult_6_28b;
  reg  [27:0] mult_7_28b;
   
  reg [27:0] temp_1lev_1;  //流水线加法寄存结果
  reg [27:0] temp_1lev_2;
  reg [27:0] temp_1lev_3;
  reg [27:0] temp_1lev_4;
  reg [27:0] temp_2lev_1;
  reg [27:0] temp_2lev_2;
  reg [27:0] last_result;
 
  wire [15:0] dout; 
  
  parameter [15:0]  h0_16b = 16'h0000;  //抽头系数
  parameter [15:0]  h1_16b = 16'h0065;  
  parameter [15:0]  h2_16b = 16'h018F;  
  parameter [15:0]  h3_16b = 16'h035A;  
  parameter [15:0]  h4_16b = 16'h0579;  
  parameter [15:0]  h5_16b = 16'h078E;  
  parameter [15:0]  h6_16b = 16'h0935;
  parameter [15:0]  h7_16b = 16'h0A1F;   
 

//------------------------------------------------
//  移位寄存器单元
//------------------------------------------------
  always @(posedge clock or posedge reset)
      if (reset)
          begin
              din_reg_00_8b <= 8'b0;
              din_reg_01_8b <= 8'b0;
              din_reg_02_8b <= 8'b0;
              din_reg_03_8b <= 8'b0;
              din_reg_04_8b <= 8'b0;
              din_reg_05_8b <= 8'b0;
              din_reg_06_8b <= 8'b0;
              din_reg_07_8b <= 8'b0;
              din_reg_08_8b <= 8'b0;
              din_reg_09_8b <= 8'b0;
              din_reg_10_8b <= 8'b0;
              din_reg_11_8b <= 8'b0;
              din_reg_12_8b <= 8'b0;
              din_reg_13_8b <= 8'b0;
              din_reg_14_8b <= 8'b0;
          end
      else
          begin
              din_reg_00_8b <= din;
              din_reg_01_8b <= din_reg_00_8b;
              din_reg_02_8b <= din_reg_01_8b;
              din_reg_03_8b <= din_reg_02_8b;
              din_reg_04_8b <= din_reg_03_8b;
              din_reg_05_8b <= din_reg_04_8b;
              din_reg_06_8b <= din_reg_05_8b;
              din_reg_07_8b <= din_reg_06_8b;
              din_reg_08_8b <= din_reg_07_8b;
              din_reg_09_8b <= din_reg_08_8b;
              din_reg_10_8b <= din_reg_09_8b;
              din_reg_11_8b <= din_reg_10_8b;
              din_reg_12_8b <= din_reg_11_8b;
              din_reg_13_8b <= din_reg_12_8b;
              din_reg_14_8b <= din_reg_13_8b;
          end           
              
//---------------------------------------------------------------------------------------------
//  预相加单元  
//---------------------------------------------------------------------------------------------     
  always @(posedge clock or posedge reset)
      if (reset) 
          begin
              sum_0_9b <= 9'b0;
              sum_1_9b <= 9'b0;
              sum_2_9b <= 9'b0;
              sum_3_9b <= 9'b0;
              sum_4_9b <= 9'b0;
              sum_5_9b <= 9'b0;
              sum_6_9b <= 9'b0;
              sum_7_9b <= 9'b0;
          end
      else
          begin
              sum_0_9b <= {din[7],           din          } + {din_reg_14_8b[7], din_reg_14_8b};
              sum_1_9b <= {din_reg_00_8b[7], din_reg_00_8b} + {din_reg_13_8b[7], din_reg_13_8b};
              sum_2_9b <= {din_reg_01_8b[7], din_reg_01_8b} + {din_reg_12_8b[7], din_reg_12_8b};
              sum_3_9b <= {din_reg_02_8b[7], din_reg_02_8b} + {din_reg_11_8b[7], din_reg_11_8b};
              sum_4_9b <= {din_reg_03_8b[7], din_reg_03_8b} + {din_reg_10_8b[7], din_reg_10_8b};
              sum_5_9b <= {din_reg_04_8b[7], din_reg_04_8b} + {din_reg_09_8b[7], din_reg_09_8b};
              sum_6_9b <= {din_reg_05_8b[7], din_reg_05_8b} + {din_reg_08_8b[7], din_reg_08_8b};
              sum_7_9b <= {din_reg_06_8b[7], din_reg_06_8b} + {din_reg_07_8b[7], din_reg_07_8b};
          end
        
//--------------------------------
//  乘法器单元  
//--------------------------------                           
  mult mult_0(
              //input
              .clock(clock),
              .dataa(h0_16b),
              .datab(sum_0_9b),
              //output
              .result(mult_0_25b)
              );
  
  mult mult_1(
              //input
              .clock(clock),
              .dataa(h1_16b),
              .datab(sum_1_9b),
              //output
              .result(mult_1_25b)
              );
  
  mult mult_2(
              //input
              .clock(clock),
              .dataa(h2_16b),
              .datab(sum_2_9b),
              //output
              .result(mult_2_25b)
              );              

  mult mult_3(
              //input
              .clock(clock),
              .dataa(h3_16b),
              .datab(sum_3_9b),
              //output
              .result(mult_3_25b)
              );              

  mult mult_4(
              //input
              .clock(clock),
              .dataa(h4_16b),
              .datab(sum_4_9b),
              //output
              .result(mult_4_25b)
              );

  mult mult_5(
              //input
              .clock(clock),
              .dataa(h5_16b),
              .datab(sum_5_9b),
              //output
              .result(mult_5_25b)
              );

  mult mult_6(
              //input
              .clock(clock),
              .dataa(h6_16b),
              .datab(sum_6_9b),
              //output
              .result(mult_6_25b)
              );

  mult mult_7(
              //input
              .clock(clock),
              .dataa(h7_16b),
              .datab(sum_7_9b),
              //output
              .result(mult_7_25b)
              );
	
		        
    always @(posedge clock or posedge reset)
		if (reset)
			begin
				mult_0_28b <= 0;
				mult_1_28b <= 0;
				mult_2_28b <= 0;
				mult_3_28b <= 0;
				mult_4_28b <= 0;
				mult_5_28b <= 0;
				mult_6_28b <= 0;
				mult_7_28b <= 0;
			end
		else
			begin
				mult_0_28b	<=	{{3{mult_0_25b[24]}}, mult_0_25b};
				mult_1_28b	<=	{{3{mult_1_25b[24]}}, mult_1_25b};
				mult_2_28b	<=	{{3{mult_2_25b[24]}}, mult_2_25b};
				mult_3_28b	<=	{{3{mult_3_25b[24]}}, mult_3_25b};
				mult_4_28b	<=	{{3{mult_4_25b[24]}}, mult_4_25b};
				mult_5_28b	<=	{{3{mult_5_25b[24]}}, mult_5_25b};
				mult_6_28b	<=	{{3{mult_6_25b[24]}}, mult_6_25b};
				mult_7_28b	<=	{{3{mult_7_25b[24]}}, mult_7_25b};
			end

//----------------------------------------------------------
//  第一级流水线加法  
//---------------------------------------------------------- 
  always @(posedge clock or posedge reset)
      if (reset)
          begin
              temp_1lev_1 <= 28'b0;
              temp_1lev_2 <= 28'b0;
              temp_1lev_3 <= 28'b0;
              temp_1lev_4 <= 28'b0; 
          end
      else
          begin
              temp_1lev_1 <= mult_0_28b + mult_1_28b;
              temp_1lev_2 <= mult_2_28b + mult_3_28b;
              temp_1lev_3 <= mult_4_28b + mult_5_28b;
              temp_1lev_4 <= mult_6_28b + mult_7_28b;
          end
          
//-----------------------------------------------------------------
//  第二级流水线加法  
//----------------------------------------------------------------- 
  always @(posedge clock or posedge reset)
      if (reset)
          begin
              temp_2lev_1 <= 28'b0;
              temp_2lev_2 <= 28'b0;
          end
      else
          begin
              temp_2lev_1 <= temp_1lev_1 + temp_1lev_2;
              temp_2lev_2 <= temp_1lev_3 + temp_1lev_4;
          end             

//---------------------------------------------------------------
//  第三级流水线加法  
//-------------------------------- ------------------------------
  always @(posedge clock or posedge reset)
      if (reset)
          last_result <= 28'b0;
      else
          last_result <= temp_2lev_1 + temp_2lev_2;
          
//---------------------------------------------------------------
//  输出结果 
//--------------------------------------------------------------- 
 /* always @(posedge clock or negedge reset)
      if (reset)
          dout <= 16'b0;
      else
          dout =last_result_28b[27:12];// {last_result_28b[27],last_result_28b[25:11]};*/
  assign	dout = {last_result[27],last_result[25:11]};  
          
endmodule