dds_mcu.tan.rpt

上传一个关于DDS开发的源程序

; N/A           ; None        ; -0.714 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[31] ; clock    ;
; N/A           ; None        ; -0.714 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[30] ; clock    ;
; N/A           ; None        ; -0.714 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[29] ; clock    ;
; N/A           ; None        ; -0.714 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[28] ; clock    ;
; N/A           ; None        ; -0.714 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[27] ; clock    ;
; N/A           ; None        ; -0.714 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[26] ; clock    ;
; N/A           ; None        ; -0.714 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[25] ; clock    ;
; N/A           ; None        ; -0.714 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[24] ; clock    ;
; N/A           ; None        ; -0.714 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[23] ; clock    ;
; N/A           ; None        ; -0.714 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[22] ; clock    ;
; N/A           ; None        ; -0.715 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[21] ; clock    ;
; N/A           ; None        ; -0.715 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[20] ; clock    ;
; N/A           ; None        ; -0.715 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[19] ; clock    ;
; N/A           ; None        ; -0.715 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[18] ; clock    ;
; N/A           ; None        ; -0.715 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[17] ; clock    ;
; N/A           ; None        ; -0.715 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[16] ; clock    ;
; N/A           ; None        ; -0.715 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[15] ; clock    ;
; N/A           ; None        ; -0.715 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; clock    ;
; N/A           ; None        ; -0.715 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; clock    ;
; N/A           ; None        ; -0.715 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; clock    ;
; N/A           ; None        ; -0.716 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; clock    ;
; N/A           ; None        ; -0.716 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; clock    ;
; N/A           ; None        ; -0.718 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[9]  ; clock    ;
; N/A           ; None        ; -0.718 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[8]  ; clock    ;
; N/A           ; None        ; -0.718 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[7]  ; clock    ;
; N/A           ; None        ; -0.718 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[6]  ; clock    ;
; N/A           ; None        ; -0.718 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[5]  ; clock    ;
; N/A           ; None        ; -0.718 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[4]  ; clock    ;
; N/A           ; None        ; -0.718 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[3]  ; clock    ;
; N/A           ; None        ; -0.718 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[2]  ; clock    ;
; N/A           ; None        ; -0.718 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[1]  ; clock    ;
; N/A           ; None        ; -0.718 ns ; SS      ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[0]  ; clock    ;
; N/A           ; None        ; -4.018 ns ; shiftin ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[0]  ; clock    ;
+---------------+-------------+-----------+---------+------------------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Mon Aug 01 11:38:50 2005
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off DDS_mcu -c DDS_mcu --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "SS" is an undefined clock
    Info: Assuming node "clock" is an undefined clock
Info: No valid register-to-register data paths exist for clock "SS"
Info: Clock "clock" Internal fmax is restricted to 275.03 MHz between source register "SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[9]" and destination register "SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[10]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.899 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y17_N7; Fanout = 2; REG Node = 'SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[9]'
            Info: 2: + IC(0.784 ns) + CELL(0.115 ns) = 0.899 ns; Loc. = LC_X12_Y17_N6; Fanout = 2; REG Node = 'SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[10]'
            Info: Total cell delay = 0.115 ns ( 12.79 % )
            Info: Total interconnect delay = 0.784 ns ( 87.21 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clock" to destination register is 2.954 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clock'
                Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X12_Y17_N6; Fanout = 2; REG Node = 'SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[10]'
                Info: Total cell delay = 2.180 ns ( 73.80 % )
                Info: Total interconnect delay = 0.774 ns ( 26.20 % )
            Info: - Longest clock path from clock "clock" to source register is 2.954 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clock'
                Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X13_Y17_N7; Fanout = 2; REG Node = 'SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[9]'
                Info: Total cell delay = 2.180 ns ( 73.80 % )
                Info: Total interconnect delay = 0.774 ns ( 26.20 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[0]" (data pin = "shiftin", clock pin = "clock") is 4.070 ns
    Info: + Longest pin to register delay is 6.987 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_214; Fanout = 1; PIN Node = 'shiftin'
        Info: 2: + IC(5.397 ns) + CELL(0.115 ns) = 6.987 ns; Loc. = LC_X13_Y17_N2; Fanout = 2; REG Node = 'SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[0]'
        Info: Total cell delay = 1.590 ns ( 22.76 % )
        Info: Total interconnect delay = 5.397 ns ( 77.24 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clock" to destination register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clock'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X13_Y17_N2; Fanout = 2; REG Node = 'SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[0]'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
Info: tco from clock "SS" to destination pin "q[0]" through register "DFF_MCU:inst1|lpm_ff:lpm_ff_component|dffs[0]" is 8.028 ns
    Info: + Longest clock path from clock "SS" to source register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 64; CLK Node = 'SS'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X14_Y15_N2; Fanout = 1; REG Node = 'DFF_MCU:inst1|lpm_ff:lpm_ff_component|dffs[0]'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.850 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y15_N2; Fanout = 1; REG Node = 'DFF_MCU:inst1|lpm_ff:lpm_ff_component|dffs[0]'
        Info: 2: + IC(2.742 ns) + CELL(2.108 ns) = 4.850 ns; Loc. = PIN_84; Fanout = 0; PIN Node = 'q[0]'
        Info: Total cell delay = 2.108 ns ( 43.46 % )
        Info: Total interconnect delay = 2.742 ns ( 56.54 % )
Info: th for register "SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[31]" (data pin = "SS", clock pin = "clock") is -0.714 ns
    Info: + Longest clock path from clock "clock" to destination register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clock'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X10_Y17_N8; Fanout = 1; REG Node = 'SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[31]'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 3.683 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 64; CLK Node = 'SS'
        Info: 2: + IC(1.347 ns) + CELL(0.867 ns) = 3.683 ns; Loc. = LC_X10_Y17_N8; Fanout = 1; REG Node = 'SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[31]'
        Info: Total cell delay = 2.336 ns ( 63.43 % )
        Info: Total interconnect delay = 1.347 ns ( 36.57 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Aug 01 11:38:53 2005
    Info: Elapsed time: 00:00:06