dds_mcu.tan.rpt

上传一个关于DDS开发的源程序

Timing Analyzer report for DDS_mcu
Mon Aug 01 11:38:54 2005
Version 4.2 Build 157 12/07/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clock'
  6. tsu
  7. tco
  8. th
  9. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                   ;
+------------------------------+-------+---------------+------------------------------------------------+-----------------------------------------------------+------------------------------------------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                                    ; From                                                ; To                                                   ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+-----------------------------------------------------+------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 4.070 ns                                       ; shiftin                                             ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[0]  ;            ; clock    ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 8.028 ns                                       ; DFF_MCU:inst1|lpm_ff:lpm_ff_component|dffs[0]       ; q[0]                                                 ; SS         ;          ; 0            ;
; Worst-case th                ; N/A   ; None          ; -0.714 ns                                      ; SS                                                  ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[22] ;            ; clock    ; 0            ;
; Clock Setup: 'clock'         ; N/A   ; None          ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; clock      ; clock    ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;                                                     ;                                                      ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+-----------------------------------------------------+------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minumum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Clock Analysis Only                                   ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Do Min/Max analysis using Rise/Fall delays            ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Use Clock Latency for PLL offset                      ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; SS              ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; clock           ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock'                                                                                                                                                                                                                                                             ;
+-------+------------------------------------------------+------------------------------------------------------+------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                                                 ; To                                                   ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------------------------------------------------------+------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[9]  ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; clock      ; clock    ; None                        ; None                      ; 0.899 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[21] ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[22] ; clock      ; clock    ; None                        ; None                      ; 0.888 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; clock      ; clock    ; None                        ; None                      ; 0.874 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; clock      ; clock    ; None                        ; None                      ; 0.842 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[5]  ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[6]  ; clock      ; clock    ; None                        ; None                      ; 0.838 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[27] ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[28] ; clock      ; clock    ; None                        ; None                      ; 0.838 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[6]  ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[7]  ; clock      ; clock    ; None                        ; None                      ; 0.835 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[23] ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[24] ; clock      ; clock    ; None                        ; None                      ; 0.835 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[4]  ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[5]  ; clock      ; clock    ; None                        ; None                      ; 0.834 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[16] ; SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[17] ; clock      ; clock    ; None                        ; None                      ; 0.834 ns                ;