arraycheck.map.rpt

在QuartusII运用ＡＨＤＬ语言

+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Total logic elements              ; 43      ;
; Total combinational functions     ; 34      ;
;     -- Total 4-input functions    ; 11      ;
;     -- Total 3-input functions    ; 5       ;
;     -- Total 2-input functions    ; 7       ;
;     -- Total 1-input functions    ; 11      ;
;     -- Total 0-input functions    ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 34      ;
; Total logic cells in carry chains ; 11      ;
; I/O pins                          ; 28      ;
; Maximum fan-out node              ; Clock   ;
; Maximum fan-out                   ; 34      ;
; Total fan-out                     ; 185     ;
; Average fan-out                   ; 2.61    ;
+-----------------------------------+---------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                       ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |arraycheck                ; 43 (43)     ; 34           ; 0           ; 28   ; 0            ; 9 (9)        ; 9 (9)             ; 25 (25)          ; 11 (11)         ; |arraycheck         ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------+
; State Machine - |arraycheck|SMA                                                                   ;
+----------+----------+--------+---------+---------+----------+--------+--------+--------+----------+
; Name     ; Ao_seven ; Az_six ; Ao_five ; Az_four ; Az_three ; Az_two ; Az_one ; A_zero ; az_eight ;
+----------+----------+--------+---------+---------+----------+--------+--------+--------+----------+
; A_zero   ; 0        ; 0      ; 0       ; 0       ; 0        ; 0      ; 0      ; 0      ; 0        ;
; Az_one   ; 0        ; 0      ; 0       ; 0       ; 0        ; 0      ; 1      ; 1      ; 0        ;
; Az_two   ; 0        ; 0      ; 0       ; 0       ; 0        ; 1      ; 0      ; 1      ; 0        ;
; Az_three ; 0        ; 0      ; 0       ; 0       ; 1        ; 0      ; 0      ; 1      ; 0        ;
; Az_four  ; 0        ; 0      ; 0       ; 1       ; 0        ; 0      ; 0      ; 1      ; 0        ;
; Ao_five  ; 0        ; 0      ; 1       ; 0       ; 0        ; 0      ; 0      ; 1      ; 0        ;
; Az_six   ; 0        ; 1      ; 0       ; 0       ; 0        ; 0      ; 0      ; 1      ; 0        ;
; Ao_seven ; 1        ; 0      ; 0       ; 0       ; 0        ; 0      ; 0      ; 1      ; 0        ;
; az_eight ; 0        ; 0      ; 0       ; 0       ; 0        ; 0      ; 0      ; 1      ; 1        ;
+----------+----------+--------+---------+---------+----------+--------+--------+--------+----------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 34    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 22    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; Poly[0]~reg                            ; 14      ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/PLD作业/研二队-戴振华(S20051003)第4次作业/text7.3PN-arraycheck/arraycheck.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed Jan 11 13:57:10 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off arraycheck -c arraycheck
Info: Found 1 design units, including 1 entities, in source file arraycheck.tdf
    Info: Found entity 1: arraycheck
Info: Elaborating entity "arraycheck" for the top level hierarchy
Info: State machine "|arraycheck|SMA" contains 9 states and 4 state bits
Info: Selected Auto state machine encoding method for state machine "|arraycheck|SMA"
Info: Encoding result for state machine "|arraycheck|SMA"
    Info: Completed encoding using 9 state bits
        Info: Encoded state bit "Ao_seven"
        Info: Encoded state bit "Az_six"
        Info: Encoded state bit "Ao_five"
        Info: Encoded state bit "Az_four"
        Info: Encoded state bit "Az_three"
        Info: Encoded state bit "Az_two"
        Info: Encoded state bit "Az_one"
        Info: Encoded state bit "A_zero"
        Info: Encoded state bit "az_eight"
    Info: State "|arraycheck|A_zero" uses code string "000000000"
    Info: State "|arraycheck|Az_one" uses code string "000000110"
    Info: State "|arraycheck|Az_two" uses code string "000001010"
    Info: State "|arraycheck|Az_three" uses code string "000010010"
    Info: State "|arraycheck|Az_four" uses code string "000100010"
    Info: State "|arraycheck|Ao_five" uses code string "001000010"
    Info: State "|arraycheck|Az_six" uses code string "010000010"
    Info: State "|arraycheck|Ao_seven" uses code string "100000010"
    Info: State "|arraycheck|az_eight" uses code string "000000011"
Info: Registers with preset signals will power-up high
Info: Implemented 71 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 26 output pins
    Info: Implemented 43 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Wed Jan 11 13:57:17 2006
    Info: Elapsed time: 00:00:08