arraycheck.tan.rpt

在QuartusII运用ＡＨＤＬ语言

; tco                                                                                ;
+-------+--------------+------------+-------------------+---------------+------------+
; Slack ; Required tco ; Actual tco ; From              ; To            ; From Clock ;
+-------+--------------+------------+-------------------+---------------+------------+
; N/A   ; None         ; 7.285 ns   ; Poly[7]~reg       ; Poly[7]       ; Clock      ;
; N/A   ; None         ; 7.283 ns   ; Poly[8]~reg       ; Poly[8]       ; Clock      ;
; N/A   ; None         ; 7.019 ns   ; Exactarray[0]~reg ; Exactarray[0] ; Clock      ;
; N/A   ; None         ; 7.008 ns   ; Exactarray[3]~reg ; Exactarray[3] ; Clock      ;
; N/A   ; None         ; 7.008 ns   ; Exactarray[2]~reg ; Exactarray[2] ; Clock      ;
; N/A   ; None         ; 6.915 ns   ; Poly[6]~reg       ; Poly[6]       ; Clock      ;
; N/A   ; None         ; 6.894 ns   ; Poly[5]~reg       ; Poly[5]       ; Clock      ;
; N/A   ; None         ; 6.890 ns   ; Poly[4]~reg       ; Poly[4]       ; Clock      ;
; N/A   ; None         ; 6.887 ns   ; Poly[9]~reg       ; Poly[9]       ; Clock      ;
; N/A   ; None         ; 6.883 ns   ; Poly[2]~reg       ; Poly[2]       ; Clock      ;
; N/A   ; None         ; 6.878 ns   ; Poly[0]~reg       ; Poly[0]       ; Clock      ;
; N/A   ; None         ; 6.713 ns   ; Count[0]~reg      ; Count[0]      ; Clock      ;
; N/A   ; None         ; 6.712 ns   ; Count[7]~reg      ; Count[7]      ; Clock      ;
; N/A   ; None         ; 6.705 ns   ; Count[4]~reg      ; Count[4]      ; Clock      ;
; N/A   ; None         ; 6.687 ns   ; Count[6]~reg      ; Count[6]      ; Clock      ;
; N/A   ; None         ; 6.679 ns   ; Count[5]~reg      ; Count[5]      ; Clock      ;
; N/A   ; None         ; 6.594 ns   ; Exactarray[1]~reg ; Exactarray[1] ; Clock      ;
; N/A   ; None         ; 6.576 ns   ; Poly[1]~reg       ; Poly[1]       ; Clock      ;
; N/A   ; None         ; 6.571 ns   ; Poly[3]~reg       ; Poly[3]       ; Clock      ;
; N/A   ; None         ; 6.570 ns   ; Poly[10]~reg      ; Poly[10]      ; Clock      ;
; N/A   ; None         ; 6.444 ns   ; Count[8]~reg      ; Count[8]      ; Clock      ;
; N/A   ; None         ; 6.396 ns   ; Count[1]~reg      ; Count[1]      ; Clock      ;
; N/A   ; None         ; 6.260 ns   ; Count[10]~reg     ; Count[10]     ; Clock      ;
; N/A   ; None         ; 6.259 ns   ; Count[9]~reg      ; Count[9]      ; Clock      ;
; N/A   ; None         ; 6.259 ns   ; Count[3]~reg      ; Count[3]      ; Clock      ;
; N/A   ; None         ; 6.259 ns   ; Count[2]~reg      ; Count[2]      ; Clock      ;
+-------+--------------+------------+-------------------+---------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed Jan 11 13:57:36 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off arraycheck -c arraycheck --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "Clock" is an undefined clock
Info: Clock "Clock" has Internal fmax of 231.32 MHz between source register "Poly[0]~reg" and destination register "Exactarray[2]~reg" (period= 4.323 ns)
    Info: + Longest register to register delay is 4.062 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y10_N3; Fanout = 14; REG Node = 'Poly[0]~reg'
        Info: 2: + IC(1.250 ns) + CELL(0.114 ns) = 1.364 ns; Loc. = LC_X23_Y10_N6; Fanout = 2; COMB Node = 'Exactarray[0]~461'
        Info: 3: + IC(0.466 ns) + CELL(0.590 ns) = 2.420 ns; Loc. = LC_X23_Y10_N3; Fanout = 3; COMB Node = 'Exactarray[0]~462'
        Info: 4: + IC(0.477 ns) + CELL(0.114 ns) = 3.011 ns; Loc. = LC_X23_Y10_N5; Fanout = 2; COMB Node = 'Exactarray[2]~465'
        Info: 5: + IC(0.444 ns) + CELL(0.607 ns) = 4.062 ns; Loc. = LC_X23_Y10_N8; Fanout = 3; REG Node = 'Exactarray[2]~reg'
        Info: Total cell delay = 1.425 ns ( 35.08 % )
        Info: Total interconnect delay = 2.637 ns ( 64.92 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "Clock" to destination register is 2.781 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 34; CLK Node = 'Clock'
            Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X23_Y10_N8; Fanout = 3; REG Node = 'Exactarray[2]~reg'
            Info: Total cell delay = 2.180 ns ( 78.39 % )
            Info: Total interconnect delay = 0.601 ns ( 21.61 % )
        Info: - Longest clock path from clock "Clock" to source register is 2.781 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 34; CLK Node = 'Clock'
            Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X21_Y10_N3; Fanout = 14; REG Node = 'Poly[0]~reg'
            Info: Total cell delay = 2.180 ns ( 78.39 % )
            Info: Total interconnect delay = 0.601 ns ( 21.61 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "Clock" to destination pin "Poly[7]" through register "Poly[7]~reg" is 7.285 ns
    Info: + Longest clock path from clock "Clock" to source register is 2.781 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 34; CLK Node = 'Clock'
        Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X21_Y10_N5; Fanout = 3; REG Node = 'Poly[7]~reg'
        Info: Total cell delay = 2.180 ns ( 78.39 % )
        Info: Total interconnect delay = 0.601 ns ( 21.61 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.280 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y10_N5; Fanout = 3; REG Node = 'Poly[7]~reg'
        Info: 2: + IC(2.156 ns) + CELL(2.124 ns) = 4.280 ns; Loc. = PIN_104; Fanout = 0; PIN Node = 'Poly[7]'
        Info: Total cell delay = 2.124 ns ( 49.63 % )
        Info: Total interconnect delay = 2.156 ns ( 50.37 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Jan 11 13:57:37 2006
    Info: Elapsed time: 00:00:01