📄 pcic_t.tdf
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--jot OR (LR_PXFR and lt_abortn and not TS_DISC and not lt_rdynR and direct_xfr)
--jot ) and frame and irdy) -- END of 2nd LCELL
--jot OR (LCELL(
--jot (LR_PXFR and lt_abortn and not TS_DISC and lt_rdynR)
--jot ) and frame and not irdy);-- END of 3rd LCELL
-- OR (LR_PXFR and (lt_abortn and frame and not TS_DISC) and (lt_rdynR) and (not irdy) and (direct_xfr)
-- OR (LR_PXFR and (lt_abortn and frame and not TS_DISC) and (lt_rdynR) and (not irdy) and (not direct_xfr)
--------- LR_PXFR Register-OR Optimization ----------------------------------------------------
LR_PXFR_r1.clk = clk;
LR_PXFR_r1.clrn = rstn;
LR_PXFR_r1_d_lc1 = LCELL(not TS_DISC and not lt_rdynR and direct_xfr);
LR_PXFR_r1_d_lc2 = LCELL(
(LR_LXFR and lt_abortn and lt_discn and LR_PXFR_r1_d_lc1)
);
LR_PXFR_r1_d_lc3 = LCELL(
(LR_PXFR and lt_abortn and not TS_DISC and lt_rdynR)
);
LR_PXFR_r1_d = LR_PXFR_r1_d_lc2
OR (LR_PXFR_r1_d_lc3 and frame and not irdy);-- END of 3rd LCELL
LR_PXFR_r1.d = LR_PXFR_r1_d;
LR_PXFR_r2.clk = clk;
LR_PXFR_r2.clrn = rstn;
LR_PXFR_r2_d_lc1 = LCELL((LR_PXFR_32 %and trdy_or% and lt_abortn)
OR (LR_WAIT and lt_abortn));
LR_PXFR_r2_d_lc2 = LCELL(
LR_PXFR_r2_d_lc1
OR (LR_PXFR and lt_abortn and LR_PXFR_r1_d_lc1)
);
LR_PXFR_r2_d = (LR_PXFR_r2_d_lc2 and frame and irdy); -- END of 2nd LCELL
LR_PXFR_r2.d = LR_PXFR_r2_d;
LR_PXFR = LR_PXFR_r1.q OR LR_PXFR_r2.q;
LR_PXFR_d = LR_PXFR_r1_d OR LR_PXFR_r2_d;
--------- LR_WAIT_d Optimization --------------------------------------------------------------
--LR_WAIT_d = (LR_PXFR and not (not lt_abortn or not frame or TS_DISC) and (not irdy and not lt_rdynR and direct_xfr))
-- OR (LR_WAIT and not (not lt_abortn or not frame) and not (irdy));
--LR_WAIT_d = (LR_PXFR and lt_abortn and not TS_DISC and not lt_rdynR and direct_xfr and frame and not irdy )
-- OR (LR_WAIT and lt_abortn and frame and not irdy);
LR_WAIT_lc1 = LCELL(not TS_DISC and not lt_rdynR and direct_xfr);
LR_WAIT_lc2 = LCELL(
(LR_PXFR and lt_abortn and LR_WAIT_lc1)
OR (LR_WAIT and lt_abortn)
);
LR_WAIT_d = LR_WAIT_lc2 and frame and not irdy;
---------- LR_WAIT_32_d Optimization -------------------------------------------------------
--LR_WAIT_32_d = (LR_PXFR and not (not lt_abortn or not frame or TS_DISC)
-- and not (not irdy and not lt_rdynR and direct_xfr)
-- and not (irdy and lt_rdynR)
-- and (not irdy and not lt_rdynR and not direct_xfr))
-- OR (LR_WAIT_32 and not (not lt_abortn or not frame) and not (irdy));
--LR_WAIT_32_d = (LR_PXFR and (lt_abortn and frame and not TS_DISC) and (not irdy and not lt_rdynR and not direct_xfr))
-- and (irdy or lt_rdynR or not direct_xfr)
-- and (not irdy or not lt_rdynR)
-- OR (LR_WAIT_32 and (lt_abortn and frame) and (not irdy));
LR_WAIT_32_lc1 = LCELL(not TS_DISC and not lt_rdynR and not direct_xfr);
LR_WAIT_32_lc2 = LCELL(
(LR_PXFR and lt_abortn and LR_WAIT_32_lc1)
OR (LR_WAIT_32 and lt_abortn)
);
LR_WAIT_32_d = --(LR_PXFR and (lt_abortn and frame and not TS_DISC) and (not irdy and not lt_rdynR and not direct_xfr))
-- and (irdy or lt_rdynR or not direct_xfr)
-- and (not irdy or not lt_rdynR)
LR_WAIT_32_lc2 and frame and not irdy;
--------- LR_DONE_d Optimization -----------------------------------------------------------
--LR_DONE_d = (LR_LXFR and (not lt_abortn or not lt_discn OR TS_DISC))
-- OR (LR_PXFR_32 and (not lt_abortn OR not frame))
-- OR (LR_PXFR AND (not lt_abortn or not frame or TS_DISC) )
-- OR (LR_WAIT and (not lt_abortn or not frame))
-- OR (LR_WAIT_32 and (not lt_abortn or not frame));
LR_DONE_d = LCELL (
(LR_LXFR and (not lt_abortn or not lt_discn OR TS_DISC))
)
OR LCELL (
(LR_PXFR_32 and not lt_abortn)
OR (LR_PXFR AND (not lt_abortn or TS_DISC))
OR (LR_WAIT and not lt_abortn)
OR (LR_WAIT_32 and not lt_abortn)
)
OR LCELL (
(LR_PXFR_32)
OR (LR_PXFR)
OR (LR_WAIT)
OR (LR_WAIT_32)
) and not frame;
END GENERATE;
--*****************************SIGNALS***************************************
-- Local Target Data Transfer Signal
lt_dxfrn = !(!lt_rdynR & (!lt_ackn %or not lt_lackn or not lt_hackn%)); -- Target data transfer is occurring
-- lt_dxfrn = !((!lt_rdynR & !lt_ackn) or (LW_LXFR and not TS_DXFR)); -- Target data transfer is occurring
-- Registered version of Local Target Ready
lt_rdynR = lt_rdyn;
lt_rdynR.clk = clk;
lt_rdynR.prn = rstn;
lt_rdynR_R = lt_rdynR;
lt_rdynR_R.clk = clk;
lt_rdynR_R.prn = rstn;
-- Target Transaction Status Registers
lt_tsr[11..0] = ( dac_sr.q and not TS_IDLE,
pxfr,
(burst_trans.q and not TS_IDLE),-- and not mstr_actv),
targ_access, -- 8: Target is accessed from PCI bus
(64_trans.q and not TS_IDLE), -- 7: Target transaction is 64 bit
exp_rom_hit, -- 6: I/O cycle indicator
base_hit[5..0] -- 5..0: Target Base Address Register accessed
);
-- Expansion ROM base hit
exp_rom_hit = gnd;
-- Indicates a Burst Transaction
burst_trans.clk = clk;
burst_trans.prn = VCC;
burst_trans.clrn = rstn;
burst_trans.s = irdy and frame ;-- and not TS_IDLE;
burst_trans.r = LCELL((TS_TURN_AR or mstr_actv) or (TS_IDLE));
-- Targ_access is equivalent to lt_framen from PCI_B
-- targ_access = (TS_ADR_CLMD OR TS_DXFR OR TS_TURN_AR OR LW_DONE) AND not cfg_cyc;
targ_access = not TS_IDLE;
-- Data time out error indicates that data was in the pipe, but there was a timeout and data is now lost
data_timeout_error = gnd;
-- Indicates a 64 bit transaction
req64_R.clk = clk;
req64_R.clrn = rstn;
req64_R.d = req64;-- and (TS_IDLE and targ_trig);
64_trans.clk = clk;
64_trans.clrn = rstn;
64_trans.prn = VCC;
64_trans_set = LCELL(req64_R and adr_phase and not cfg_cyc and not io_cyc);-- and not TS_IDLE);
64_trans_rst_lc1 = LCELL(((LW_DONE or LR_DONE) and not TS_DISC) or tabrt_rcvd_set);
64_trans_rst_lc2 = LCELL(serr_sig_set or mstr_abrt_set --tmbw64_serr.scf, mmbr64_serr.scf
or (mstr_actv and lm_ackn));
64_trans.s = 64_trans_set;--not cfg_cyc and not io_cyc;-- and not mstr_actv;
-- 64_trans.s = req64 and not cfg_cyc and not io_cyc and not TS_IDLE;
64_trans.r = (-- Target Write disconnect
64_trans_rst_lc1
or 64_trans_rst_lc2);
-- or cfg_cyc
-- or io_cyc;
--jot 64_trans.r = TS_TURN_AR;
64_trans_or = 64_trans.q and not cfg_cyc and not io_cyc and not TS_IDLE;
64_trans_out = 64_trans.q;
fast_back.clk = clk;
fast_back.clrn = rstn;
fast_back.prn = VCC;
-- fast_back.s = frame_i1r and not frame_ir and frame;
fast_back.s = TS_TURN_AR and frame;
fast_back.r = TS_TURN_AR;
--**************
-- If any of these conditions is true, read Cycle should Stop.
rd_backoff = (not lt_abortn or not lt_discn or TS_DISC);
bar_hit_rst = TS_TURN_AR;
pxfr.clk = clk;
pxfr.clrn = rstn;
pxfr.d = ((TS_DXFR or TS_DISC) and irdy and trdy_out);
-- State Machine Outputs
TURN_AR_R.clk = clk; -- Turn Around State Delayed One clock
TURN_AR_R.clrn = rstn;
TURN_AR_R.d = TS_TURN_AR;
-- lt_rdyn Input Register
--jot lt_rdy_IR.clk = clk;
--jot lt_rdy_IR.clrn = rstn;
--jot lt_rdy_IR.d = NOT lt_rdyn;
-- Configuration Address Decode Enable
-- May be able to delay it by one clock.
cfg_adr_dec_ena_lc1 = LCELL(TS_IDLE and idsel_IR and (ad_ir_address[1..0] == B"00"));
cfg_adr_dec_ena_lc2 = LCELL(cben_IR_address[3..1] == B"101");
cfg_adr_dec_ena = LCELL( adr_phase and cfg_adr_dec_ena_lc1
and cfg_adr_dec_ena_lc2);
-- cfg_adr_dec_ena = TS_IDLE and adr_phase and idsel_IR
-- and (cben_IR_address[3..1] == B"101")
-- and (ad_ir_address[1..0] == B"00");
-- Retry will be signaled if lt_discn is active druing TS_ADR_VLD
-- state and the access is not configuration access
-- Also a retry will be signaled if the local side has not cleared
-- the write data pipeline.
retry.clk = clk;
retry.clrn = rstn;
retry_set = LCELL(NOT lt_discn OR lreg_busy or not lt_abortn);
retry_rst_lc1 = LCELL((LW_DONE OR LW_IDLE) and lt_discn and lt_abortn);
retry_rst_lc2 = LCELL(TS_IDLE and retry_rst_lc1 and not adr_phase);
retry.s = retry_set; -- Added (not lt_abortn) to assert stopn one clock after devseln
-- if lt_abortn is asserted on TS_ADR_VLD
retry.r = retry_rst_lc2;
-- Registered lt_discn
lt_discnR.clk = clk;
lt_discnR.clrn = rstn;
lt_discnR.d = lt_discn;
-- Access Cycle Indicators
IF (CAP_LIST_ENA == "NO") GENERATE
cfg_cyc.clk = clk;
cfg_cyc.clrn = rstn;
cfg_cyc.s = adr_phase and idsel_IR and (cben_IR_address[3..1] == B"101");
cfg_cyc.r = TS_IDLE and not adr_phase;
mem_cyc.clk = clk;
mem_cyc.clrn = rstn;
-- mem_cyc.s = adr_phase and ( (cben_IR_address[3..1] == B"011")
-- or (cben_IR_address[3..1] == B"110")
-- or (cben_IR_address[3..2] == B"11"));
mem_cyc.s = adr_phase and (
( cben_IR_address[3..1] == B"011" )
or ( cben_IR_address[3..0] == B"1100")
or ( cben_IR_address[3..1] == B"111" )
);
mem_cyc.r = TS_IDLE and not adr_phase;
cap_ptr_ena_sr.clk = clk;
cap_ptr_ena_sr.clrn = rstn;
cap_ptr_ena_sr.s = GND;
cap_ptr_ena_sr.r = VCC;
-- cap_ptr_ena = LCELL((ad_ir_address[6] or ad_ir_address[7] or ad_ir_address[8] or ad_ir_address[9] OR ad_ir_address[10])
-- and adr_phase and idsel_IR and (cben_IR_address[3..1] == B"101"));
cap_ptr_ena_lc1 = GND;
cap_ptr_ena_lc2 = GND;
cap_ptr_ena = GND;
io_cyc.clk = clk;
io_cyc.clrn = rstn;
io_cyc.s = adr_phase and (cben_IR_address[3..1] == B"001");
io_cyc.r = TS_IDLE and not adr_phase;
ELSE GENERATE
assert report "Instantiating Capabilities Pointer"
severity info;
cfg_cyc.clk = clk;
cfg_cyc.clrn = rstn;
cfg_cyc.s = adr_phase and idsel_IR and (cben_IR_address[3..1] == B"101") and (ad_ir_address[10..6]==B"00000");
cfg_cyc.r = TS_IDLE and not adr_phase;
mem_cyc.clk = clk;
mem_cyc.clrn = rstn;
-- mem_cyc.s = adr_phase and ( (cben_IR_address[3..1] == B"011")
-- or (cben_IR_address[3..1] == B"110")
-- or (cben_IR_address[3..2] == B"11")
-- or (idsel_IR and (cben_IR_address[3..1] == B"101") and not(ad_ir_address[10..6]==B"00000")));
mem_cyc.s = adr_phase and (
( cben_IR_address[3..1] == B"011" )
or ( cben_IR_address[3..0] == B"1100")
or ( cben_IR_address[3..1] == B"111" )
);
mem_cyc.r = TS_IDLE and not adr_phase;
cap_ptr_ena_sr.clk = clk;
cap_ptr_ena_sr.clrn = rstn;
cap_ptr_ena_sr.s = cap_ptr_ena;
cap_ptr_ena_sr.r = TS_IDLE and not adr_phase;
cap_ptr_ena_lc1 = LCELL(ad_ir_address[6] or ad_ir_address[8] or ad_ir_address[9] OR ad_ir_address[10]);
cap_ptr_ena_lc2 = LCELL(idsel_IR and (cben_IR_address[3..1] == B"101"));
cap_ptr_ena = LCELL(( ad_ir_address[7] or cap_ptr_ena_lc1)
and adr_phase_lc1 and cap_ptr_ena_lc2);
io_cyc.clk = clk;
io_cyc.clrn = rstn;
io_cyc.s = adr_phase and (cben_IR_address[3..1] == B"001");
io_cyc.r = TS_IDLE and not adr_phase;
END GENERATE;
wr_rdn_FF.clk = clk;
wr_rdn_FF.clrn = rstn;
wr_rdn_FF.prn = vcc;
wr_rdn_FF.s = adr_phase AND (cben_IR_address[1..0] == B"11" )
AND LW_IDLE;
wr_rdn_FF.r = TS_IDLE AND LW_IDLE;
wr_rdn = wr_rdn_FF.q;
-- lreg_busy : Register indicating that the local side has not retrieved all
-- the write data and next target accesses should be retried, Except for
-- Configuration Cycles
lreg_busy.clk = clk;
lreg_busy.clrn = rstn;
lreg_busy.s = NOT LW_IDLE and NOT LW_DONE;
lreg_busy.r = (LW_DONE and TS_IDLE) OR LW_IDLE; -- ??
targ_trig_lc1 = LCELL(not ad_ir_address1 and not ad_ir_address0 and not cben_ir_address2 and idsel_IR);
targ_trig_lc2 = LCELL(adr_phase and cben_ir_address3 and cben_ir_address1);
targ_trig = LCELL((targ_trig_lc2 and targ_trig_lc1) or mem_bar_hit);
-- targ_trig =
-- (adr_phase and idsel_IR and (cben_IR_address[3..1] == B"101") and (ad_ir_address[1..0] == B"00"))
-- or (mem_bar_hit);
-- Configuration Data valid on AD_IR[31..0] Used to enable the read/Write registers
-- In the configuration space
cfg_dat_vld = TS_TURN_AR AND cfg_cyc AND wr_rdn ;
-- AD/CBE Input Register Enable
-- ad_IR_ce_A = LCELL (
-- (TS_IDLE and not adr_phase and not cfg_cyc)
-- or (TS_IDLE and cben_ir_address[3..1]==B"101")
-- );
-- ad_IR_ce_D = LCELL (
-- ((TS_ADR_CLMD # TS_DXFR # TS_ADR_VLD # TS_DISC) and not LW_WAIT)
-- or (TS_TURN_AR and cfg_cyc)
-- ); -- Data enable during configuration write
-- cben_IR_ce_A = LCELL (
-- (TS_IDLE and not adr_phase and not cfg_cyc)
-- or (TS_IDLE and cben_ir_address[3..1]==B"101")
-- );
-- cben_IR_ce_D = LCELL (
-- ((⌨️ 快捷键说明
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