pcic_t.tdf

来自「PCI logicore,在某网站上下载的ip核文件」· TDF 代码 · 共 1,849 行 · 第 1/5 页

TDF
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	cfg.lcfg_adr[7..0]			=	lcfg_adr[7..0];			-- Local Configuration Address
	cfg.lcfg_ben[3..0]			=	lcfg_ben[3..0];			-- Local Configuration Byte enables
	cfg.lcfg_dat_in[31..0]		=	lcfg_dat_in[31..0];		-- Local Configuration Data Input Bus
	cfg.lcfg_adr_vld			=	lcfg_adr_vld;			-- Local Configuration Address Valid
	cfg.lcfg_dat_vld			=	lcfg_dat_vld;			-- Local Configuration data Valid
	lcfg_dat_out[31..0]			=	cfg.lcfg_dat_out[31..0];-- Local Configuration Data Output


--	**********************************************************************
--	****			END Instatiate of Config.tdf				****
--	**********************************************************************


-- Configuration Status Register error conditions
	
	tabrt_sig_cyc.clk	= clk;
	tabrt_sig_cyc.clrn	= rstn;
	tabrt_sig_cyc.prn	= VCC;
	tabrt_sig_cyc.s		= tabrt_set;
	tabrt_sig_cyc.r		= TS_ADR_VLD;
	
	tabrt_set			= not lt_abortn;	-- Signaled Target Abort
	tabrt_rcvd_set		= targ_abrt_set;	-- Recieved Target Abort

-- Target Control State Machine

IF (OPTIMIZE_TARG == "NO") GENERATE

	Assert REPORT "NOT OPTIMIZING TARGET"
	Severity Warning;

	targ_sm.clk		= clk;
	targ_sm.reset	= !rstn;

	CASE targ_sm IS
		WHEN TS_IDLE	=>	IF targ_trig then					-- Address Hit one Of BARs 
							targ_sm = TS_ADR_VLD ;
						ELSE
							targ_sm = TS_IDLE;
						END IF;
						
		-- Address Valid State, Turn on Otput Drivers			
		WHEN TS_ADR_VLD	=> 	IF serr_sig_set	then					-- Address Parity Error Detected
							targ_sm = TS_IDLE;
	--					ELSIF (not lt_abortn and not cfg_cyc) THEN	-- Abort Signaled -- Devsel must be asserted at least one clock cycle
	--						targ_sm = TS_DISC;
						ELSE
							targ_sm = TS_ADR_CLMD;			-- Goto Address Claimed State
						END IF;
		
		WHEN TS_ADR_CLMD	=>	-- If retry, Disconnect, Abort is signaled in I/O or Mem Cycle
						IF (((retry or not lt_discn or not lt_abortn) and not cfg_cyc) or mstr_actv) THEN	
							targ_sm = TS_DISC;
						ELSIF ((not lt_rdyn) or cfg_cyc)		THEN		-- Memory Write Cycle
							targ_sm = TS_DXFR;
						ELSE
							targ_sm = TS_ADR_CLMD;		
						END IF;
						
		-- Transfer Data state
		WHEN	TS_DXFR	=>	IF (not lt_abortn or not lt_discn) Then	-- Disconnect or Abort Signaled
							targ_sm = TS_DISC;
						ELSIF (   (not frame and trdy_OR)	) THEN-- Normal Master Termination Detected
							 	
							targ_sm = TS_TURN_AR;
						ELSE
							targ_sm = TS_DXFR;
						END IF;
						
		
		-- Wait for Data to be recieved from Local Side during a read
		WHEN TS_LRD_WAIT 	=>	IF (not lt_abortn OR not lt_discn) THEN		-- Abort or Retry is signaled from Local Side
							targ_sm = TS_DISC;
						ELSIF (LR_PXFR) 			THEN		-- One Word is recieved from Local Side during Mem Cycle
							targ_sm = TS_DXFR;	
						ELSE		
							targ_sm = TS_LRD_WAIT;			-- No Words Have been recieved and termination is not signaled
						END IF;
						
		-- Disconnect State, Retry, Abort, Disconnect
		WHEN TS_DISC	=>	IF (not frame) Then				-- Master Terminated transactions
							targ_sm = TS_TURN_AR;
						ELSE
							targ_sm = TS_DISC;				-- Master Did not terminate transaction
						END IF;
		
		-- Turn around State
		WHEN TS_TURN_AR	=> 	targ_sm = TS_IDLE;

	
	END CASE ;

%
	TS_IDLE = not TS_IDLE_not;

	TS_IDLE_d = (TS_IDLE and not targ_trig)
				OR (TS_ADR_VLD and  serr_sig_set)
				OR (TS_TURN_AR);

	TS_ADR_VLD_d = (TS_IDLE and targ_trig);

	TS_ADR_CLMD_d = (TS_ADR_VLD and not serr_sig_set)
					OR (TS_ADR_CLMD and not ((retry or not lt_discn or not lt_abortn) and not cfg_cyc) and not ((not lt_rdyn) or cfg_cyc));

	TS_DXFR_d = (TS_ADR_CLMD and not ((retry or not lt_discn or not lt_abortn) and not cfg_cyc) and ((not lt_rdyn) or cfg_cyc))
				OR (TS_DXFR and not (not lt_abortn or not lt_discn) and not (not frame and trdy_OR))
				OR (TS_LRD_WAIT and not (not lt_abortn OR not lt_discn) and LR_PXFR);

	TS_LRD_WAIT_d = (TS_LRD_WAIT and not (not lt_abortn OR not lt_discn) and not LR_PXFR);

	TS_DISC_d = (TS_ADR_CLMD and ((retry or not lt_discn or not lt_abortn) and not cfg_cyc))
				OR (TS_DXFR and (not lt_abortn or not lt_discn))	
				OR (TS_LRD_WAIT and (not lt_abortn OR not lt_discn))
				OR (TS_DISC and not (not frame));

	TS_TURN_AR_d = (TS_DXFR and not (not lt_abortn or not lt_discn) and (not frame and trdy_OR))
					OR (TS_DISC and (not frame));
%		
	

	lw_sm.clk	= clk;
	lw_sm.reset	= NOT rstn;

---********

	CASE lw_sm IS
		WHEN LW_IDLE => 	IF (TS_ADR_CLMD and not lt_rdyn and not cfg_cyc and wr_rdn and not serr_sig_set and lt_abortn and not retry) THEN	-- Only triggered in I/O or Mem Cycles and retry is not signaled
						lw_sm = LW_LXFR;
						LW_LXFR_d = VCC;
					ELSE
						lw_sm = LW_IDLE;
						LW_IDLE_d = VCC;
					END IF;
% Oliver Tan 1-11-99					
		-- Pipe Has no data 
		WHEN LW_LXFR =>	IF (not TS_DXFR) THEN						-- Pipe is empty and targ_sm is finished
						lw_sm = LW_DONE;
						LW_DONE_d = VCC;
					ELSIF (lt_rdyn and TS_DXFR and lt_ack_or) THEN						-- pipe is full and local is waiting
						lw_sm = LW_WAIT;
						LW_WAIT_d = VCC;
					ELSE
						lw_sm = LW_LXFR;												-- data is being transferred through pipe
						LW_LXFR_d = VCC;
					END IF;
					
		-- Pipe Has Data	But Local Side is asserting Wait			
		WHEN LW_WAIT => 	IF (data_timeout_error) THEN							--  PCI has completed the transaction
								lw_sm = LW_DONE;									--  but local side asserted wait for
								LW_DONE_d = VCC;									--  too long
							ELSIF ((not lt_rdyn and TS_DXFR) or TS_TURN_AR) THEN
								lw_sm = LW_LXFR;									-- Local is still asserting wait
								LW_LXFR_d = VCC;
							ELSE
								lw_sm = LW_WAIT;									-- Pipe is not empty and local xferring data
								LW_WAIT_d = VCC;

							END IF;
%

		-- Pipe Has no data 
		WHEN LW_LXFR =>	--jot  IF (not lt_rdyn and not TS_DXFR) THEN						-- Pipe is empty and targ_sm is finished
						IF (not lt_rdyn %and not TS_DXFR% and TS_DISC and irdy) THEN			-- Pipe is empty and targ_sm is finished
						lw_sm = LW_DONE;											-- tmbw64_disc_2f.scf
						LW_DONE_d = VCC;
					ELSIF (TS_TURN_AR) THEN											-- Pipe is empty and targ_sm is finished
						lw_sm = LW_DONE;											-- tmbw32_64_1pw_1a.scf
						LW_DONE_d = VCC;
--					ELSIF (lt_rdyn and (%lt_ack_OR and% %lt_low_ack_OR or lt_hi_ack_OR or% irdy)) THEN		-- Ored lt_ack_or and irdy to account for wait state on first data phase  -- pipe is full and local is waiting
					ELSIF (lt_rdyn and irdy and not TS_DISC) THEN		-- Ored lt_ack_or and irdy to account for wait state on first data phase  -- pipe is full and local is waiting					
						lw_sm = LW_WAIT;
						LW_WAIT_d = VCC;
					ELSE
						lw_sm = LW_LXFR;												-- data is being transferred through pipe
						LW_LXFR_d = VCC;
					END IF;
					
		-- Pipe Has Data	But Local Side is asserting Wait			
		WHEN LW_WAIT => 	IF (data_timeout_error) THEN							--  PCI has completed the transaction
								lw_sm = LW_DONE;									--  but local side asserted wait for
								LW_DONE_d = VCC;									--  too long
							ELSIF (lt_rdyn) THEN
								lw_sm = LW_WAIT;									-- Local is still asserting wait
								LW_WAIT_d = VCC;
							ELSIF (not lt_rdyn AND not TS_DXFR) THEN				-- Pipe is empty and no more data 
								lw_sm = LW_DONE;
								LW_DONE_d = VCC;
							ELSE
								lw_sm = LW_LXFR;									-- Pipe is not empty and local xferring data
								LW_LXFR_d = VCC;
							END IF;

					
		-- Pipe is empty and Local Side recieve all Data and PCI completed Transaction
		WHEN LW_DONE =>  lw_sm = LW_IDLE;
					LW_IDLE_d = VCC;
	
	END CASE;




	lr_sm.clk	= clk;
	lr_sm.reset	= not rstn;

	CASE lr_sm IS

		-- TS_IDLE State
		WHEN LR_IDLE	=> 	IF (TS_ADR_VLD and not wr_rdn and not cfg_cyc and not retry 
							and not serr_sig_set and lt_abortn and lt_discn ) THEN	-- Begining of I/O or Mem Read Cycle is detected
							lr_sm = LR_LXFR;							-- Go to the local Transfer State
							LR_LXFR_d = VCC;
						ELSE
							lr_sm = LR_IDLE;
							LR_IDLE_d = VCC;
						END IF;
						
		-- Local Xfr state.  Wait for local side to transfer First DWORD
		WHEN LR_LXFR	=> 	
						IF (not lt_abortn or not lt_discn OR TS_DISC) THEN		-- Local Side signaled ABORT or DISCONNECT
							lr_sm	= LR_DONE;						-- Local DONE
							LR_DONE_d = VCC;
						ELSIF (not lt_rdynR and direct_xfr) THEN						-- Local Side transferred the First Word
							lr_sm = LR_PXFR;
							LR_PXFR_d = VCC;
						ELSIF (not lt_rdynR and not direct_xfr) THEN
							lr_sm = LR_PXFR_32;
							LR_PXFR_32_d = VCC;
						ELSE
							lr_sm = LR_LXFR;						-- Wait for word to xferred from Local side
							LR_LXFR_d = VCC;
						END IF;

		-- Local PCI transfer for 64 bit local to 32 bti PCI
		-- Transfer the low bits
		WHEN LR_PXFR_32 =>		
						IF (not lt_abortn OR not frame) THEN
							lr_sm = LR_DONE;
							LR_DONE_d = VCC;
						ELSIF (irdy) THEN
							lr_sm = LR_PXFR;
							LR_PXFR_d = VCC;
						ELSE
							lr_sm = LR_PXFR_32;
							LR_PXFR_32_d = VCC;
						END IF;
					
		-- PCI XFR State, Pipe has One Words in it
		-- For 64->64 all bits are transferred, for 64->32 the high bits are transfered in this state
		WHEN LR_PXFR	=>
					 	IF (not lt_abortn or not frame or TS_DISC) THEN			-- Target Abort or Normal Termination by master
							lr_sm	= LR_DONE;
							LR_DONE_d = VCC;
						ELSIF (not irdy and not lt_rdynR and direct_xfr)  THEN			-- PCI side asserted wait states but local side transferred 
							lr_sm = LR_WAIT;						-- additional words
							LR_WAIT_d = VCC;
						ELSIF (irdy and lt_rdynR) THEN				-- PCI side accepted data and local side did not xfr data
							lr_sm = LR_LXFR;						-- more data to send to PCI
							LR_LXFR_d = VCC;
						ELSIF (not irdy and not lt_rdynR and not direct_xfr) THEN
							lr_sm = LR_WAIT_32;
							LR_WAIT_32_d = VCC;
						ELSIF (irdy and not lt_rdynR and not direct_xfr) THEN
							lr_sm = LR_PXFR_32;
							LR_PXFR_32_d = VCC;
						ELSE
							lr_sm = LR_PXFR;
							LR_PXFR_d = VCC;
						END IF;


		-- PCI Wait State, Pipe has Two 64 bit Words in it
		-- Wait for IRDY
		WHEN LR_WAIT	=>
					 	IF (not lt_abortn or not frame) THEN			-- Local Side signaled an abort or PCI is done
							lr_sm	= LR_DONE;
							LR_DONE_d = VCC;
						ELSIF(irdy ) THEN					-- Detected wait is ending and other data is in pipe
							lr_sm = LR_PXFR;
							LR_PXFR_d = VCC;
						ELSE
							lr_sm = LR_WAIT;
							LR_WAIT_d = VCC;
						END IF;

		-- PCI 32 bit Wait State, Pipe has Three 32 bit Words in it
		-- For 64->32 the low bits of the previous word is transferred in this state
		WHEN LR_WAIT_32 =>
						IF (not lt_abortn or not frame) THEN
							lr_sm = LR_DONE;
							LR_DONE_d = VCC;
						ELSIF (irdy) THEN
							lr_sm = LR_PXFR_32;
							LR_PXFR_32_d = VCC;
						ELSE 
							lr_sm = LR_WAIT_32;
							LR_WAIT_32_d = VCC;
						END IF;
						
		WHEN LR_DONE	=> 	lr_sm = LR_IDLE;
							LR_IDLE_d = VCC;

		
	END CASE;
%
LR_WAIT_32_d = (LR_PXFR and not (not lt_abortn or not frame or TS_DISC) 
					and not (not irdy and not lt_rdynR and direct_xfr) 
					and not (not irdy and not lt_rdynR and direct_xfr)
					and not (irdy and lt_rdynR)
					and (not irdy and not lt_rdynR and not direct_xfr))
				OR
			(LR_WAIT_32 and not (not lt_abortn or not frame) and not (irdy));
%
%
LR_IDLE = not LR_IDLE_not;

LR_IDLE_d = (LR_IDLE and not (TS_ADR_VLD and not wr_rdn and not cfg_cyc and not retry and not serr_sig_set and lt_abortn and lt_discn) )
			OR (LR_DONE);

LR_LXFR_d = (LR_IDLE and (TS_ADR_VLD and not wr_rdn and not cfg_cyc and not retry and not serr_sig_set and lt_abortn and lt_discn ))
			OR (LR_LXFR and not (not lt_abortn or not lt_discn OR TS_DISC) and not (not lt_rdynR and direct_xfr) and not (not lt_rdynR and not direct_xfr))
			OR (LR_PXFR and not (not lt_abortn or not frame or TS_DISC)  and not (not irdy and not lt_rdynR and direct_xfr) and (irdy and lt_rdynR));

LR_PXFR_32_d = (LR_LXFR and not (not lt_abortn or not lt_discn OR TS_DISC) and not (not lt_rdynR and direct_xfr) and (not lt_rdynR and not direct_xfr) )
			OR (LR_PXFR_32 and not (not lt_abortn OR not frame) and not (irdy))
			OR (LR_PXFR and not (not lt_abortn or not frame or TS_DISC) and not (not irdy and not lt_rdynR and direct_xfr) and not (irdy and lt_rdynR) and not (not irdy and not lt_rdynR and not direct_xfr) and (irdy and not lt_rdynR and not direct_xfr) )
			OR (LR_WAIT_32 and not (not lt_abortn or not frame) and (irdy));

LR_PXFR_d = (LR_LXFR and not (not lt_abortn or not lt_discn OR TS_DISC) and (not lt_rdynR and direct_xfr))
			OR (LR_PXFR_32 and not (not lt_abortn OR not frame) and (irdy))
			OR (LR_PXFR and not (not lt_abortn or not frame or TS_DISC) and not (not irdy and not lt_rdynR and direct_xfr) and not (irdy and lt_rdynR) and not (not irdy and not lt_rdynR and not direct_xfr) and not (irdy and not lt_rdynR and not direct_xfr) )
			OR (LR_WAIT and not (not lt_abortn or not frame) and (irdy) ) ;

LR_WAIT_d = (LR_PXFR and not (not lt_abortn or not frame or TS_DISC) and (not irdy and not lt_rdynR and direct_xfr))
			OR (LR_WAIT and not (not lt_abortn or not frame) and not (irdy));

LR_WAIT_32_d = (LR_PXFR and not (not lt_abortn or not frame or TS_DISC) and not (not irdy and not lt_rdynR and direct_xfr) and not (irdy and lt_rdynR) and (not irdy and not lt_rdynR and not direct_xfr))
				OR (LR_WAIT_32 and not (not lt_abortn or not frame) and not (irdy));

LR_DONE_d = (LR_LXFR and (not lt_abortn or not lt_discn OR TS_DISC))
			OR (LR_PXFR_32 and (not lt_abortn OR not frame)) 
			OR (LR_PXFR AND (not lt_abortn or not frame or TS_DISC) )
			OR (LR_WAIT and (not lt_abortn or not frame))
			OR (LR_WAIT_32 and (not lt_abortn or not frame));     
%




ELSE GENERATE

	Assert REPORT "-------- *** OPTIMIZING TARGET *** ----------"
	Severity Debug;

	
-- Target State Machine


	(TS_IDLE_not, 		
	TS_ADR_VLD, 	
	TS_ADR_CLMD, 	
	TS_DXFR, 					
	TS_LRD_WAIT, 	
	TS_DISC, 		
	TS_TURN_AR).clk		= clk;


	(TS_IDLE_not, 		
	TS_ADR_VLD, 	
	TS_ADR_CLMD, 	

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