📄 pcic_t.tdf
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-- LR_PXFR_32,
LR_WAIT_32 : DFFE;
LR_IDLE,
LR_IDLE_d,
-- LR_PXFR_d,
LR_LXFR_d,
LR_WAIT_d,
LR_DONE_d,
-- LR_PXFR_32_d,
LR_WAIT_32_d : NODE;
LR_PXFR_32_r1 : DFFE;
LR_PXFR_32_r2 : DFFE;
LR_PXFR_32 : NODE;
LR_PXFR_32_r1_d : NODE;
LR_PXFR_32_r2_d : NODE;
LR_PXFR_32_d : NODE;
LR_PXFR_32_hi_low_sel_lc1 : NODE;
LR_PXFR_32_hi_low_sel_lc2 : NODE;
-- LR_PXFR_32_r1_lc1 : NODE;
LR_PXFR_r1 : DFFE;
LR_PXFR_r2 : DFFE;
LR_PXFR : NODE;
LR_PXFR_r1_d : NODE;
LR_PXFR_r2_d : NODE;
LR_PXFR_d : NODE;
LR_WAIT_lc1 : NODE;
LR_WAIT_lc2 : NODE;
LR_WAIT_32_lc1 : NODE;
LR_WAIT_32_lc2 : NODE;
LR_PXFR_r1_d_lc1 : NODE;
LR_PXFR_r1_d_lc2 : NODE;
LR_PXFR_r1_d_lc3 : NODE;
LR_PXFR_r2_d_lc1 : NODE;
LR_PXFR_r2_d_lc2 : NODE;
LR_PXFR_32_r1_d_lc1 : NODE;
LR_PXFR_32_r1_d_lc2 : NODE;
LR_PXFR_32_r1_d_lc3 : NODE;
LR_PXFR_32_r2_d_lc1 : NODE;
LR_LXFR_d_lc1 : NODE;
LR_LXFR_d_lc2 : NODE;
LR_LXFR_d_lc3 : NODE;
LR_LXFR_d_lc4 : NODE;
LR_LXFR_d_lc5 : NODE;
LR_LXFR_d_lc6 : NODE;
END GENERATE;
retry : SRFF; -- Retry Indicator
retry_set : NODE;
retry_rst_lc1 : NODE;
retry_rst_lc2 : NODE;
lt_discnR : DFFE; -- Registered version of lt_discn wr_rdn : NODE; -- Data Cycle type
wr_rdn_FF : pcic_sr; -- Data Cycle type mem_cyc : SRFF; -- Memory Cycle Indicator
wr_rdn : NODE;
mem_cyc : SRFF;
cfg_cyc : SRFF; -- Configuration Cycle Indicator
io_cyc : SRFF; -- I/O Cycle Indicator
cfg_dat_vld : NODE;
cfg_adr_dec_ena : NODE; -- Enable Configuration Address Decoder
cfg_adr_dec_ena_lc1 : NODE; -- Enable Configuration Address Decoder
cfg_adr_dec_ena_lc2 : NODE; -- Enable Configuration Address Decoder
lreg_busy : SRFF; -- Local Side did not finish emptying the Write Pipeline
-- lt_frame_OR : SRFF; -- Local Targer Frame Output Register
-- lt_frame_or_rst : NODE;
-- lt_frame_or_set : NODE;
lt_frame_OR : SRFF; -- Local Targer Frame Output Register
lt_frame_or_rst : NODE;
lt_frame_or_rst_lc1 :NODE;
lt_frame_or_rst_lc2 :NODE;
lt_frame_or_rst_lc3 :NODE;
lt_frame_or_rst_lc4 :NODE;
lt_frame_or_set : NODE;
cap_ptr_ena : NODE;
cap_ptr_ena_lc1 : NODE;
cap_ptr_ena_lc2 : NODE;
cap_ptr_ena_sr : SRFF;
adoe : DFFE;
TURN_AR_R : DFFE;
--jot lt_rdy_IR : DFFE; -- lt_rdy Active High Input Register
pxfr : DFFE; -- This indicates that a PCI transferr has just occurred, Rising
-- edge when trdyn and irdyn are low will result in this going high
bar_hit_rst : NODE; -- This will reset the BAR_HIT after the current cycle is complete
rd_backoff : NODE; -- Indicates that Read Cycle should be stopped.
-- stop_lc[2..1] : NODE;
-- trdy_lc[7..2] : NODE;
-- trdy_lc1 : NODE;
trdy_lc[5..1] : LCELL;
trdy_lc1_1a : NODE;
trdy_lc1_1b : NODE;
trdy_lc1_1c : NODE;
trdy_lc1_1d : NODE;
trdy_lc1_1e : NODE;
trdy_lc1_2e : NODE;
trdy_lc1_1f : NODE;
trdy_lc1_1g : NODE;
trdy_lc1_1h : NODE;
trdy_lc1_1i : NODE;
trdy_lc1_1j : NODE;
trdy_lc1_1k : NODE;
trdy_lc1_1m : NODE;
trdy_hi_low_lc1 : NODE;
trdy_hi_low_lc2 : NODE;
trdy_lc3_1a : NODE;
trdy_lc3_1b : NODE;
trdy_lc4_1a : NODE;
trdy_lc5_1a : NODE;
trdy_lc5_1b : NODE;
trdy_lc5_1c : NODE;
-- stop_lc[3..1] : LCELL;
stop_lc[3..1] : LCELL;
stop_lc1_1a : LCELL;
stop_lc1_1b : LCELL;
stop_lc1_1c : LCELL;
stop_lc1_1d : LCELL;
stop_lc1_1e : LCELL;
stop_lc2_1a : LCELL;
stop_lc2_1b : LCELL;
stop_lc2_1c : LCELL;
stop_lc2_1d : LCELL;
stop_lc2_1e : LCELL;
stop_lc3_1a : LCELL;
stop_lc3_1b : LCELL;
lt_ack_R_r1 : DFFE; -- Local Target Acknowledge Register 1 Signal
lt_ack_R_r1_lc1 : NODE;
lt_ack_R_r1_lc2 : NODE;
lt_ack_R_r1_lc3 : NODE;
lt_ack_R_r1_lc4 : NODE;
lt_ack_R_r1_lc5 : NODE;
lt_ack_R_r1_lc6 : NODE;
lt_ack_R_r1_lc7 : NODE;
lt_ack_R_r1_lc8 : NODE;
lt_ack_R_r1_lc9 : NODE;
lt_ack_R_r1_lc10 : NODE;
lt_ack_R_r1_lc11 : NODE;
lt_ack_R_r2 : DFFE; -- Local Target Acknowledge Register 2 Signal
lt_ack_R_r2_lc1 : NODE;
lt_ack_R_r2_lc2 : NODE;
lt_ack_R_r2_lc3 : NODE;
lt_ack_R_r2_lc4 : NODE;
lt_ack_R_r2_lc5 : NODE;
lt_ack_R_r2_lc6 : NODE;
lt_ack_R_r2_lc7 : NODE;
lt_ack_R_r3 : DFFE; -- Local Target Acknowledge Register 2 Signal
lt_ack_R_r3_lc1 : NODE;
lt_ack_R_r3_lc2 : NODE;
lt_ack_R_r3_lc2a : NODE;
lt_ack_R_r3_lc2b : NODE;
lt_ack_R_r3_lc3 : NODE;
lt_ack_R_r3_lc4 : NODE;
lt_ack_R_r3_lc5 : NODE;
lt_ack_R : NODE; -- Local Target Acknowledge Signal
lt_ack_OR : NODE; -- Local Target Acknowledge Output Register
-- lt_ack_R : DFFE; -- Local Target Acknowledge Signal
-- lt_ack_R_r1 : DFFE; -- Local Target Acknowledge Register 1 Signal
-- lt_ack_R_r2 : DFFE; -- Local Target Acknowledge Register 2 Signal
-- lt_ack_R_r3 : DFFE; -- Local Target Acknowledge Register 2 Signal
-- lt_ack_R : NODE; -- Local Target Acknowledge Signal
-- lt_ack_OR : NODE; -- Local Target Acknowledge Output Register
-- lt_low_ack_R : DFFE; -- Local Target Low Acknowledge Signal
-- lt_low_ack_OR : NODE; -- Local Target Low Acknowledge Output Register
-- lt_hi_ack_R : DFFE; -- Local Target High Acknowledge Signal
-- lt_hi_ack_OR : NODE; -- Local Target High Acknowledge Output Register
data_timeout_error : NODE; -- Indicates a data timeout error
lt_rdynR : DFFE; -- Register version of local target ready
lt_rdynR_R : DFFE;
targ_access : NODE;
EXP_ROM_HIT : NODE;
trg_OR_advance : DFFE;
lt_ldata_ack : NODE; -- Target local output Data Acknowledge -- Low
lt_ldata_ack_lc1 : NODE;
lt_lack : TFFE; -- Local Target toggle flop to determine where the data is valid
lt_lack_lc1 : NODE;
lt_hdata_ack : NODE; -- Target local output Data Acknowledge -- High
lt_hdata_ack_R : DFFE;
lt_ldata_ack_R : DFFE;
-- lt_ldata_ack_RR : DFFE;
64_trans : pcic_sr; -- 64 bit transaction indicator
64_trans_rst_lc1 : NODE;
64_trans_rst_lc2 : NODE;
64_trans_set : NODE;
fast_back : pcic_sr;
direct_xfr : LCELL;--node; -- Target Read State Machine path
burst_trans : pcic_sr; -- Burst Transaction
dati_hr_ena_lc : NODE;
dac_cfg : NODE; -- To check during configuration time whether system placed target in the 32 memory space although
-- requested 64-bit memory space (for 2Gbytes and less memory size)
hi_low_sel_lc1 : NODE;
hi_low_sel_lc2 : NODE;
hi_low_sel_d1 : DFFE;
hi_low_sel_d1_lc1 : NODE;
hi_low_sel_d1_lc1a : NODE;
hi_low_sel_d1_lc2 : NODE;
hi_low_sel_d1_lc3 : NODE;
hi_low_sel_d1_lc4 : NODE;
hi_low_sel_d1_lc5 : NODE;
hi_low_sel_d1_lc5a : NODE;
hi_low_sel_d1_lc6 : NODE;
hi_low_sel_d2 : DFFE;
hi_low_sel_d2_lc1 : NODE;
hi_low_sel_d2_lc2 : NODE;
hi_low_sel_d2_lc3 : NODE;
hi_low_sel_d2_lc4 : NODE;
hi_low_sel_d2_lc5 : NODE;
hi_low_sel_d2_lc6 : NODE;
hi_low_sel_d3 : DFFE;
hi_low_sel_d3_lc1 : NODE;
hi_low_sel_d3_lc2 : NODE;
WAIT_wait32 : DFFE;
ador_hi_dena_lc : NODE;
BEGIN
junk = junk or io_bar_hit or mstr_actv or lr_wait_32_d or mem_cyc or lw_idle_d or pxfr
or lr_idle_d or lr_wait_d or lr_pxfr_d or LR_PXFR_32_d OR mstr_dac_decode
or cap_ptr_ena_lc1 or cap_ptr_ena_lc2;
-- Frame Input Register
frame_IR.clk = clk;
frame_IR.clrn = rstn;
frame_IR.d = frame;
-- IRDYN Input Register
irdyRn.clk = clk;
irdyRn.clrn = rstn;
irdyRn.d = not irdy;
-- Frame Delayed Two Clocks
frame_I1R.clk = clk;
frame_I1R.clrn = rstn;
frame_I1R.d = frame_IR;
frame_I2R.clk = clk;
frame_I2R.clrn = rstn;
frame_I2R.d = frame_I1R;
-- idsel Input Register
idsel_IR.clk = clk;
idsel_IR.clrn = rstn;
idsel_IR.d = idsel;
dac_sr.clk = clk;
dac_sr.clrn = rstn;
dac_sr.prn = VCC;
dac_sr.s = adr_phase and (cben_ir_address[3..0]==B"1101");--(cben_ir_address[3] and cben_ir_address[2] and not cben_ir_address[1] and cben_ir_address[0]);
dac_sr.r = TS_IDLE and not adr_phase;
dac_cfg = dac_sr.q;
dac_sr_out = dac_cfg;
adr_phase_lc1 = ((frame_IR and NOT frame_I1R% and not (cben_ir_address[3..0] == B"1101")%) OR (frame_I1R and NOT frame_I2R and dac_sr.q));
adr_phase = adr_phase_lc1 and not mstr_actv ;
adr_phase_out = adr_phase;
-- **********************************************************************
-- **** Instantiate the config.tdf ****
-- **********************************************************************
cfg.clk = clk; -- PCI Clock
cfg.rstn = rstn; -- PCI Reset
cfg.cben_IR[3..0] = cben_ir_data[3..0];--cben_IR_address[3..0]; -- Registered cben signals
cfg.cben_IR_addr[3..0] = cben_IR_address[3..0]; -- Registered cben signals
cfg.ad_IR[31..0] = ad_ir_data[31..0];--ad_ir_address[31..0]; -- Registered PCI Address/Data Bus
cfg.ad_ir_addr[31..0] = ad_ir_address[31..0];
cfg.adr_phase = adr_phase; -- High One Clock after Address Phase
cfg.cfg_dat_vld = cfg_dat_vld; -- Configuration Data is valid at ad_IR[31..0]
cfg.serr_det = serr_sig_set; -- Signaled SERR
cfg.adr_dec_ena = cfg_adr_dec_ena; -- Enable Configuration Address Decoder
cfg.tabrt_set = tabrt_set; -- Signaled Target Abort
cfg.tabrt_rcvd_set = tabrt_rcvd_set; -- Recieved Target Abort
cfg.mabrt_set = mstr_abrt_set; -- Recieved Master Abort
cfg.bar_hit_rst = bar_hit_rst; -- Reset the bar Hit bit at end of PCI access
cfg.perr_det_set = perr_det_set; -- Detected Parity Error
cfg.perr_rep_set = perr_rep_set; -- Data Parity Error Signaled
cfg.dac_cfg = dac_cfg;
mem_bar_hit = cfg.mem_bar_hit; -- One of the Memory BARs has Positive Address Compare
io_bar_hit = cfg.io_bar_hit; -- One of the I/O BARs has Positive Address Compare
cfg_dat_out[31..0] = cfg.cfg_dat_out[31..0];-- Configuration Data Output
-- Command Register Outputs
io_ena = cfg.io_ena; -- I/O Space Enable
mem_ena = cfg.mem_ena; -- Memory Space Enable
mstr_ena = cfg.mstr_ena; -- Bus Master Enable
mwi_ena = cfg.mwi_ena; -- Memory Write and Invalidate Enable
perr_ena = cfg.perr_ena; -- Pariy Error Response Enable
serr_ena = cfg.serr_ena; -- SERR Enable
-- dac_cfg = cfg.dac_out;
-- Status Register Outputs
cfg_perr_rep = cfg.perr_rep; -- Data Parity Error Signaled
cfg_tabrt_sig = cfg.tabrt_sig; -- Signaled Target Abort
cfg_tabrt_rcvd = cfg.tabrt_rcvd; -- Recieved Target Abort
cfg_mabrt_rcvd = cfg.mabrt_rcvd; -- Recieved Master Abort
cfg_serr_sig = cfg.serr_sig; -- Signaled SERR
cfg_perr_det = cfg.perr_det; -- Detected Parity Error
lat_dat[7..0] = cfg.lat_dat[7..0]; -- Latency Timer Register Data
cache_dat[7..0] = cfg.cache_dat[7..0]; -- Cache Line Register Data
base_hit[5..0] = cfg.base_hit[5..0]; -- Base Address Register Comparison Outputs
-- Local Side Configuration Space Support
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