foudiv.fit.qmsg

可以实现对任意波形分任意频

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jun 15 22:20:38 2007 " "Info: Processing started: Fri Jun 15 22:20:38 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off foudiv -c foudiv " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off foudiv -c foudiv" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "foudiv EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"foudiv\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "5 5 " "Info: No exact pin location assignment(s) for 5 pins of 5 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "fout " "Info: Pin fout not assigned to an exact location on the device" {  } { { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 10 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "fout" } } } } { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "" { fout } "NODE_NAME" } "" } } { "F:/EDA_Quartus/foudiv/foudiv.fld" "" { Floorplan "F:/EDA_Quartus/foudiv/foudiv.fld" "" "" { fout } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "clk " "Info: Pin clk not assigned to an exact location on the device" {  } { { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 7 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "" { clk } "NODE_NAME" } "" } } { "F:/EDA_Quartus/foudiv/foudiv.fld" "" { Floorplan "F:/EDA_Quartus/foudiv/foudiv.fld" "" "" { clk } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "rst " "Info: Pin rst not assigned to an exact location on the device" {  } { { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 9 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rst" } } } } { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "" { rst } "NODE_NAME" } "" } } { "F:/EDA_Quartus/foudiv/foudiv.fld" "" { Floorplan "F:/EDA_Quartus/foudiv/foudiv.fld" "" "" { rst } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "pclk " "Info: Pin pclk not assigned to an exact location on the device" {  } { { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 7 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "pclk" } } } } { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "" { pclk } "NODE_NAME" } "" } } { "F:/EDA_Quartus/foudiv/foudiv.fld" "" { Floorplan "F:/EDA_Quartus/foudiv/foudiv.fld" "" "" { pclk } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "clkmd " "Info: Pin clkmd not assigned to an exact location on the device" {  } { { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 8 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkmd" } } } } { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "" { clkmd } "NODE_NAME" } "" } } { "F:/EDA_Quartus/foudiv/foudiv.fld" "" { Floorplan "F:/EDA_Quartus/foudiv/foudiv.fld" "" "" { clkmd } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 29 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 29" {  } { { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 7 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "pclk Global clock in PIN 28 " "Info: Automatically promoted signal \"pclk\" to use Global clock in PIN 28" {  } { { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 7 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "rst Global clock in PIN 153 " "Info: Automatically promoted some destinations of signal \"rst\" to use Global clock in PIN 153" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "\\lammy03:dodata\[1\] " "Info: Destination \"\\lammy03:dodata\[1\]\" may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "\\lammy03:dodata\[7\] " "Info: Destination \"\\lammy03:dodata\[7\]\" may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "\\lammy03:dodata\[0\] " "Info: Destination \"\\lammy03:dodata\[0\]\" may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "\\lammy03:dodata\[5\] " "Info: Destination \"\\lammy03:dodata\[5\]\" may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "\\lammy03:dodata\[3\] " "Info: Destination \"\\lammy03:dodata\[3\]\" may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "\\lammy03:dodata\[4\] " "Info: Destination \"\\lammy03:dodata\[4\]\" may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "\\lammy03:dodata\[6\] " "Info: Destination \"\\lammy03:dodata\[6\]\" may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "\\lammy03:dodata\[2\] " "Info: Destination \"\\lammy03:dodata\[2\]\" may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "\\lammy02:updata\[1\] " "Info: Destination \"\\lammy02:updata\[1\]\" may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "\\lammy02:updata\[7\] " "Info: Destination \"\\lammy02:updata\[7\]\" may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0}  } { { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 9 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}