foudiv.tan.qmsg

可以实现对任意波形分任意频

{ "Info" "ITDB_TH_RESULT" "\\lammy03:dodata\[4\] rst clk -0.700 ns register " "Info: th for register \"\\lammy03:dodata\[4\]\" (data pin = \"rst\", clock pin = \"clk\") is -0.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.956 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.956 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 20 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 20; CLK Node = 'clk'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "" { clk } "NODE_NAME" } "" } } { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.776 ns) + CELL(0.711 ns) 2.956 ns \\lammy03:dodata\[4\] 2 REG LC_X7_Y18_N5 4 " "Info: 2: + IC(0.776 ns) + CELL(0.711 ns) = 2.956 ns; Loc. = LC_X7_Y18_N5; Fanout = 4; REG Node = '\\lammy03:dodata\[4\]'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "1.487 ns" { clk \lammy03:dodata[4] } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.75 % " "Info: Total cell delay = 2.180 ns ( 73.75 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.776 ns 26.25 % " "Info: Total interconnect delay = 0.776 ns ( 26.25 % )" {  } {  } 0}  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "2.956 ns" { clk \lammy03:dodata[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.956 ns" { clk clk~out0 \lammy03:dodata[4] } { 0.000ns 0.000ns 0.776ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.671 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.671 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rst 1 PIN PIN_153 28 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 28; PIN Node = 'rst'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "" { rst } "NODE_NAME" } "" } } { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.335 ns) + CELL(0.867 ns) 3.671 ns \\lammy03:dodata\[4\] 2 REG LC_X7_Y18_N5 4 " "Info: 2: + IC(1.335 ns) + CELL(0.867 ns) = 3.671 ns; Loc. = LC_X7_Y18_N5; Fanout = 4; REG Node = '\\lammy03:dodata\[4\]'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "2.202 ns" { rst \lammy03:dodata[4] } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns 63.63 % " "Info: Total cell delay = 2.336 ns ( 63.63 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.335 ns 36.37 % " "Info: Total interconnect delay = 1.335 ns ( 36.37 % )" {  } {  } 0}  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "3.671 ns" { rst \lammy03:dodata[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.671 ns" { rst rst~out0 \lammy03:dodata[4] } { 0.000ns 0.000ns 1.335ns } { 0.000ns 1.469ns 0.867ns } } }  } 0}  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "2.956 ns" { clk \lammy03:dodata[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.956 ns" { clk clk~out0 \lammy03:dodata[4] } { 0.000ns 0.000ns 0.776ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "3.671 ns" { rst \lammy03:dodata[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.671 ns" { rst rst~out0 \lammy03:dodata[4] } { 0.000ns 0.000ns 1.335ns } { 0.000ns 1.469ns 0.867ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jun 15 22:20:51 2007 " "Info: Processing ended: Fri Jun 15 22:20:51 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}