📄 foudiv.tan.qmsg

📁 可以实现对任意波形分任意频
💻 QMSG
📖 第 1 页 / 共 4 页
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "pclk register register db\[2\] db\[6\] 275.03 MHz Internal " "Info: Clock \"pclk\" Internal fmax is restricted to 275.03 MHz between source register \"db\[2\]\" and destination register \"db\[6\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.759 ns + Longest register register " "Info: + Longest register to register delay is 2.759 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns db\[2\] 1 REG LC_X6_Y16_N3 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y16_N3; Fanout = 5; REG Node = 'db\[2\]'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "" { db[2] } "NODE_NAME" } "" } } { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.178 ns) + CELL(0.564 ns) 1.742 ns db\[2\]~115 2 COMB LC_X6_Y16_N3 2 " "Info: 2: + IC(1.178 ns) + CELL(0.564 ns) = 1.742 ns; Loc. = LC_X6_Y16_N3; Fanout = 2; COMB Node = 'db\[2\]~115'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "1.742 ns" { db[2] db[2]~115 } "NODE_NAME" } "" } } { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 1.920 ns db\[3\]~103 3 COMB LC_X6_Y16_N4 4 " "Info: 3: + IC(0.000 ns) + CELL(0.178 ns) = 1.920 ns; Loc. = LC_X6_Y16_N4; Fanout = 4; COMB Node = 'db\[3\]~103'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "0.178 ns" { db[2]~115 db[3]~103 } "NODE_NAME" } "" } } { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 2.759 ns db\[6\] 4 REG LC_X6_Y16_N7 5 " "Info: 4: + IC(0.000 ns) + CELL(0.839 ns) = 2.759 ns; Loc. = LC_X6_Y16_N7; Fanout = 5; REG Node = 'db\[6\]'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "0.839 ns" { db[3]~103 db[6] } "NODE_NAME" } "" } } { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.581 ns 57.30 % " "Info: Total cell delay = 1.581 ns ( 57.30 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.178 ns 42.70 % " "Info: Total interconnect delay = 1.178 ns ( 42.70 % )" {  } {  } 0}  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "2.759 ns" { db[2] db[2]~115 db[3]~103 db[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.759 ns" { db[2] db[2]~115 db[3]~103 db[6] } { 0.000ns 1.178ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.178ns 0.839ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pclk destination 2.954 ns + Shortest register " "Info: + Shortest clock path from clock \"pclk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns pclk 1 CLK PIN_28 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; CLK Node = 'pclk'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "" { pclk } "NODE_NAME" } "" } } { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns db\[6\] 2 REG LC_X6_Y16_N7 5 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X6_Y16_N7; Fanout = 5; REG Node = 'db\[6\]'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "1.485 ns" { pclk db[6] } "NODE_NAME" } "" } } { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "2.954 ns" { pclk db[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { pclk pclk~out0 db[6] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pclk source 2.954 ns - Longest register " "Info: - Longest clock path from clock \"pclk\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns pclk 1 CLK PIN_28 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; CLK Node = 'pclk'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "" { pclk } "NODE_NAME" } "" } } { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns db\[2\] 2 REG LC_X6_Y16_N3 5 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X6_Y16_N3; Fanout = 5; REG Node = 'db\[2\]'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "1.485 ns" { pclk db[2] } "NODE_NAME" } "" } } { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "2.954 ns" { pclk db[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { pclk pclk~out0 db[2] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "2.954 ns" { pclk db[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { pclk pclk~out0 db[6] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "2.954 ns" { pclk db[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { pclk pclk~out0 db[2] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 20 -1 0 } }  } 0}  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "2.759 ns" { db[2] db[2]~115 db[3]~103 db[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.759 ns" { db[2] db[2]~115 db[3]~103 db[6] } { 0.000ns 1.178ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.178ns 0.839ns } } } { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "2.954 ns" { pclk db[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { pclk pclk~out0 db[6] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "2.954 ns" { pclk db[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { pclk pclk~out0 db[2] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "" { db[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { db[6] } {  } {  } } } { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 20 -1 0 } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "db\[7\] clkmd pclk 5.685 ns register " "Info: tsu for register \"db\[7\]\" (data pin = \"clkmd\", clock pin = \"pclk\") is 5.685 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.602 ns + Longest pin register " "Info: + Longest pin to register delay is 8.602 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkmd 1 PIN PIN_15 23 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_15; Fanout = 23; PIN Node = 'clkmd'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "" { clkmd } "NODE_NAME" } "" } } { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.459 ns) + CELL(0.423 ns) 7.351 ns db\[0\]~120COUT0_125 2 COMB LC_X6_Y16_N0 2 " "Info: 2: + IC(5.459 ns) + CELL(0.423 ns) = 7.351 ns; Loc. = LC_X6_Y16_N0; Fanout = 2; COMB Node = 'db\[0\]~120COUT0_125'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "5.882 ns" { clkmd db[0]~120COUT0_125 } "NODE_NAME" } "" } } { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 7.429 ns db\[0\]~95 3 COMB LC_X6_Y16_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 7.429 ns; Loc. = LC_X6_Y16_N1; Fanout = 2; COMB Node = 'db\[0\]~95'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "0.078 ns" { db[0]~120COUT0_125 db[0]~95 } "NODE_NAME" } "" } } { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 7.507 ns db\[1\]~87 4 COMB LC_X6_Y16_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 7.507 ns; Loc. = LC_X6_Y16_N2; Fanout = 2; COMB Node = 'db\[1\]~87'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "0.078 ns" { db[0]~95 db[1]~87 } "NODE_NAME" } "" } } { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 7.585 ns db\[2\]~115 5 COMB LC_X6_Y16_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.078 ns) = 7.585 ns; Loc. = LC_X6_Y16_N3; Fanout = 2; COMB Node = 'db\[2\]~115'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "0.078 ns" { db[1]~87 db[2]~115 } "NODE_NAME" } "" } } { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 7.763 ns db\[3\]~103 6 COMB LC_X6_Y16_N4 4 " "Info: 6: + IC(0.000 ns) + CELL(0.178 ns) = 7.763 ns; Loc. = LC_X6_Y16_N4; Fanout = 4; COMB Node = 'db\[3\]~103'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "0.178 ns" { db[2]~115 db[3]~103 } "NODE_NAME" } "" } } { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 8.602 ns db\[7\] 7 REG LC_X6_Y16_N8 3 " "Info: 7: + IC(0.000 ns) + CELL(0.839 ns) = 8.602 ns; Loc. = LC_X6_Y16_N8; Fanout = 3; REG Node = 'db\[7\]'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "0.839 ns" { db[3]~103 db[7] } "NODE_NAME" } "" } } { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.143 ns 36.54 % " "Info: Total cell delay = 3.143 ns ( 36.54 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.459 ns 63.46 % " "Info: Total interconnect delay = 5.459 ns ( 63.46 % )" {  } {  } 0}  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "8.602 ns" { clkmd db[0]~120COUT0_125 db[0]~95 db[1]~87 db[2]~115 db[3]~103 db[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.602 ns" { clkmd clkmd~out0 db[0]~120COUT0_125 db[0]~95 db[1]~87 db[2]~115 db[3]~103 db[7] } { 0.000ns 0.000ns 5.459ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.469ns 0.423ns 0.078ns 0.078ns 0.078ns 0.178ns 0.839ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pclk destination 2.954 ns - Shortest register " "Info: - Shortest clock path from clock \"pclk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns pclk 1 CLK PIN_28 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; CLK Node = 'pclk'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "" { pclk } "NODE_NAME" } "" } } { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns db\[7\] 2 REG LC_X6_Y16_N8 3 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X6_Y16_N8; Fanout = 3; REG Node = 'db\[7\]'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "1.485 ns" { pclk db[7] } "NODE_NAME" } "" } } { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "2.954 ns" { pclk db[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { pclk pclk~out0 db[7] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "8.602 ns" { clkmd db[0]~120COUT0_125 db[0]~95 db[1]~87 db[2]~115 db[3]~103 db[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.602 ns" { clkmd clkmd~out0 db[0]~120COUT0_125 db[0]~95 db[1]~87 db[2]~115 db[3]~103 db[7] } { 0.000ns 0.000ns 5.459ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.469ns 0.423ns 0.078ns 0.078ns 0.078ns 0.178ns 0.839ns } } } { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "2.954 ns" { pclk db[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { pclk pclk~out0 db[7] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk fout \\lammy05:cnt2 9.960 ns register " "Info: tco from clock \"clk\" to destination pin \"fout\" through register \"\\lammy05:cnt2\" is 9.960 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.914 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 5.914 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 20 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 20; CLK Node = 'clk'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "" { clk } "NODE_NAME" } "" } } { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.778 ns) + CELL(0.935 ns) 3.182 ns fullup 2 REG LC_X6_Y15_N2 1 " "Info: 2: + IC(0.778 ns) + CELL(0.935 ns) = 3.182 ns; Loc. = LC_X6_Y15_N2; Fanout = 1; REG Node = 'fullup'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "1.713 ns" { clk fullup } "NODE_NAME" } "" } } { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.274 ns) + CELL(0.292 ns) 4.748 ns full 3 COMB LC_X5_Y16_N2 1 " "Info: 3: + IC(1.274 ns) + CELL(0.292 ns) = 4.748 ns; Loc. = LC_X5_Y16_N2; Fanout = 1; COMB Node = 'full'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "1.566 ns" { fullup full } "NODE_NAME" } "" } } { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.455 ns) + CELL(0.711 ns) 5.914 ns \\lammy05:cnt2 4 REG LC_X5_Y16_N4 2 " "Info: 4: + IC(0.455 ns) + CELL(0.711 ns) = 5.914 ns; Loc. = LC_X5_Y16_N4; Fanout = 2; REG Node = '\\lammy05:cnt2'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "1.166 ns" { full \lammy05:cnt2 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.407 ns 57.61 % " "Info: Total cell delay = 3.407 ns ( 57.61 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.507 ns 42.39 % " "Info: Total interconnect delay = 2.507 ns ( 42.39 % )" {  } {  } 0}  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "5.914 ns" { clk fullup full \lammy05:cnt2 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.914 ns" { clk clk~out0 fullup full \lammy05:cnt2 } { 0.000ns 0.000ns 0.778ns 1.274ns 0.455ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.822 ns + Longest register pin " "Info: + Longest register to pin delay is 3.822 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns \\lammy05:cnt2 1 REG LC_X5_Y16_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y16_N4; Fanout = 2; REG Node = '\\lammy05:cnt2'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "" { \lammy05:cnt2 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.698 ns) + CELL(2.124 ns) 3.822 ns fout 2 PIN PIN_14 0 " "Info: 2: + IC(1.698 ns) + CELL(2.124 ns) = 3.822 ns; Loc. = PIN_14; Fanout = 0; PIN Node = 'fout'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "3.822 ns" { \lammy05:cnt2 fout } "NODE_NAME" } "" } } { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 55.57 % " "Info: Total cell delay = 2.124 ns ( 55.57 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.698 ns 44.43 % " "Info: Total interconnect delay = 1.698 ns ( 44.43 % )" {  } {  } 0}  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "3.822 ns" { \lammy05:cnt2 fout } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.822 ns" { \lammy05:cnt2 fout } { 0.000ns 1.698ns } { 0.000ns 2.124ns } } }  } 0}  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "5.914 ns" { clk fullup full \lammy05:cnt2 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.914 ns" { clk clk~out0 fullup full \lammy05:cnt2 } { 0.000ns 0.000ns 0.778ns 1.274ns 0.455ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.711ns } } } { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "3.822 ns" { \lammy05:cnt2 fout } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.822 ns" { \lammy05:cnt2 fout } { 0.000ns 1.698ns } { 0.000ns 2.124ns } } }  } 0}
⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -