foudiv.tan.qmsg

可以实现对任意波形分任意频

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 7 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "pclk " "Info: Assuming node \"pclk\" is an undefined clock" {  } { { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 7 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "pclk" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "fulldo " "Info: Detected ripple clock \"fulldo\" as buffer" {  } { { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 19 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "fulldo" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "fullup " "Info: Detected ripple clock \"fullup\" as buffer" {  } { { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 18 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "fullup" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "full " "Info: Detected gated clock \"full\" as buffer" {  } { { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 17 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "full" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register do register \\lammy02:updata\[4\] 51.13 MHz 19.558 ns Internal " "Info: Clock \"clk\" has Internal fmax of 51.13 MHz between source register \"do\" and destination register \"\\lammy02:updata\[4\]\" (period= 19.558 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.518 ns + Longest register register " "Info: + Longest register to register delay is 9.518 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns do 1 REG LC_X6_Y17_N0 21 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y17_N0; Fanout = 21; REG Node = 'do'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "" { do } "NODE_NAME" } "" } } { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.442 ns) + CELL(0.575 ns) 2.017 ns add~754COUT1_833 2 COMB LC_X5_Y15_N0 2 " "Info: 2: + IC(1.442 ns) + CELL(0.575 ns) = 2.017 ns; Loc. = LC_X5_Y15_N0; Fanout = 2; COMB Node = 'add~754COUT1_833'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "2.017 ns" { do add~754COUT1_833 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 2.097 ns add~744COUT1_834 3 COMB LC_X5_Y15_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 2.097 ns; Loc. = LC_X5_Y15_N1; Fanout = 2; COMB Node = 'add~744COUT1_834'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "0.080 ns" { add~754COUT1_833 add~744COUT1_834 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 2.177 ns add~779COUT1_835 4 COMB LC_X5_Y15_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 2.177 ns; Loc. = LC_X5_Y15_N2; Fanout = 2; COMB Node = 'add~779COUT1_835'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "0.080 ns" { add~744COUT1_834 add~779COUT1_835 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 2.257 ns add~764COUT1 5 COMB LC_X5_Y15_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 2.257 ns; Loc. = LC_X5_Y15_N3; Fanout = 2; COMB Node = 'add~764COUT1'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "0.080 ns" { add~779COUT1_835 add~764COUT1 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 2.865 ns add~767 6 COMB LC_X5_Y15_N4 3 " "Info: 6: + IC(0.000 ns) + CELL(0.608 ns) = 2.865 ns; Loc. = LC_X5_Y15_N4; Fanout = 3; COMB Node = 'add~767'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "0.608 ns" { add~764COUT1 add~767 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.096 ns) + CELL(0.718 ns) 4.679 ns add~689 7 COMB LC_X7_Y15_N4 3 " "Info: 7: + IC(1.096 ns) + CELL(0.718 ns) = 4.679 ns; Loc. = LC_X7_Y15_N4; Fanout = 3; COMB Node = 'add~689'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "1.814 ns" { add~767 add~689 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 5.300 ns add~692 8 COMB LC_X7_Y15_N6 1 " "Info: 8: + IC(0.000 ns) + CELL(0.621 ns) = 5.300 ns; Loc. = LC_X7_Y15_N6; Fanout = 1; COMB Node = 'add~692'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "0.621 ns" { add~689 add~692 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.719 ns) + CELL(0.590 ns) 6.609 ns reduce_nor~79 9 COMB LC_X6_Y15_N0 1 " "Info: 9: + IC(0.719 ns) + CELL(0.590 ns) = 6.609 ns; Loc. = LC_X6_Y15_N0; Fanout = 1; COMB Node = 'reduce_nor~79'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "1.309 ns" { add~692 reduce_nor~79 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.442 ns) 7.451 ns reduce_nor~80 10 COMB LC_X6_Y15_N7 10 " "Info: 10: + IC(0.400 ns) + CELL(0.442 ns) = 7.451 ns; Loc. = LC_X6_Y15_N7; Fanout = 10; COMB Node = 'reduce_nor~80'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "0.842 ns" { reduce_nor~79 reduce_nor~80 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.589 ns) + CELL(0.478 ns) 9.518 ns \\lammy02:updata\[4\] 11 REG LC_X5_Y17_N9 4 " "Info: 11: + IC(1.589 ns) + CELL(0.478 ns) = 9.518 ns; Loc. = LC_X5_Y17_N9; Fanout = 4; REG Node = '\\lammy02:updata\[4\]'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "2.067 ns" { reduce_nor~80 \lammy02:updata[4] } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.272 ns 44.88 % " "Info: Total cell delay = 4.272 ns ( 44.88 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.246 ns 55.12 % " "Info: Total interconnect delay = 5.246 ns ( 55.12 % )" {  } {  } 0}  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "9.518 ns" { do add~754COUT1_833 add~744COUT1_834 add~779COUT1_835 add~764COUT1 add~767 add~689 add~692 reduce_nor~79 reduce_nor~80 \lammy02:updata[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.518 ns" { do add~754COUT1_833 add~744COUT1_834 add~779COUT1_835 add~764COUT1 add~767 add~689 add~692 reduce_nor~79 reduce_nor~80 \lammy02:updata[4] } { 0.000ns 1.442ns 0.000ns 0.000ns 0.000ns 0.000ns 1.096ns 0.000ns 0.719ns 0.400ns 1.589ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.080ns 0.608ns 0.718ns 0.621ns 0.590ns 0.442ns 0.478ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.956 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.956 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 20 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 20; CLK Node = 'clk'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "" { clk } "NODE_NAME" } "" } } { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.776 ns) + CELL(0.711 ns) 2.956 ns \\lammy02:updata\[4\] 2 REG LC_X5_Y17_N9 4 " "Info: 2: + IC(0.776 ns) + CELL(0.711 ns) = 2.956 ns; Loc. = LC_X5_Y17_N9; Fanout = 4; REG Node = '\\lammy02:updata\[4\]'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "1.487 ns" { clk \lammy02:updata[4] } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.75 % " "Info: Total cell delay = 2.180 ns ( 73.75 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.776 ns 26.25 % " "Info: Total interconnect delay = 0.776 ns ( 26.25 % )" {  } {  } 0}  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "2.956 ns" { clk \lammy02:updata[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.956 ns" { clk clk~out0 \lammy02:updata[4] } { 0.000ns 0.000ns 0.776ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.956 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.956 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 20 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 20; CLK Node = 'clk'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "" { clk } "NODE_NAME" } "" } } { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.776 ns) + CELL(0.711 ns) 2.956 ns do 2 REG LC_X6_Y17_N0 21 " "Info: 2: + IC(0.776 ns) + CELL(0.711 ns) = 2.956 ns; Loc. = LC_X6_Y17_N0; Fanout = 21; REG Node = 'do'" {  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "1.487 ns" { clk do } "NODE_NAME" } "" } } { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.75 % " "Info: Total cell delay = 2.180 ns ( 73.75 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.776 ns 26.25 % " "Info: Total interconnect delay = 0.776 ns ( 26.25 % )" {  } {  } 0}  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "2.956 ns" { clk do } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.956 ns" { clk clk~out0 do } { 0.000ns 0.000ns 0.776ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "2.956 ns" { clk \lammy02:updata[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.956 ns" { clk clk~out0 \lammy02:updata[4] } { 0.000ns 0.000ns 0.776ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "2.956 ns" { clk do } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.956 ns" { clk clk~out0 do } { 0.000ns 0.000ns 0.776ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } {  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 15 -1 0 } }  } 0}  } { { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "9.518 ns" { do add~754COUT1_833 add~744COUT1_834 add~779COUT1_835 add~764COUT1 add~767 add~689 add~692 reduce_nor~79 reduce_nor~80 \lammy02:updata[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.518 ns" { do add~754COUT1_833 add~744COUT1_834 add~779COUT1_835 add~764COUT1 add~767 add~689 add~692 reduce_nor~79 reduce_nor~80 \lammy02:updata[4] } { 0.000ns 1.442ns 0.000ns 0.000ns 0.000ns 0.000ns 1.096ns 0.000ns 0.719ns 0.400ns 1.589ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.080ns 0.608ns 0.718ns 0.621ns 0.590ns 0.442ns 0.478ns } } } { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "2.956 ns" { clk \lammy02:updata[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.956 ns" { clk clk~out0 \lammy02:updata[4] } { 0.000ns 0.000ns 0.776ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" "" { Report "F:/EDA_Quartus/foudiv/db/foudiv_cmp.qrpt" Compiler "foudiv" "UNKNOWN" "V1" "F:/EDA_Quartus/foudiv/db/foudiv.quartus_db" { Floorplan "F:/EDA_Quartus/foudiv/" "" "2.956 ns" { clk do } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.956 ns" { clk clk~out0 do } { 0.000ns 0.000ns 0.776ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}