foudiv.map.qmsg

可以实现对任意波形分任意频

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jun 15 22:20:32 2007 " "Info: Processing started: Fri Jun 15 22:20:32 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off foudiv -c foudiv " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off foudiv -c foudiv" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "foudiv.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file foudiv.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 foudiv-lammy " "Info: Found design unit 1: foudiv-lammy" {  } { { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 13 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 foudiv " "Info: Found entity 1: foudiv" {  } { { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "foudiv " "Info: Elaborating entity \"foudiv\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "switch foudiv.vhd(16) " "Info: (10035) Verilog HDL or VHDL information at foudiv.vhd(16): object \"switch\" declared but not used" {  } { { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 16 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "rst foudiv.vhd(36) " "Warning: VHDL Process Statement warning at foudiv.vhd(36): signal \"rst\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 36 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "rst foudiv.vhd(51) " "Warning: VHDL Process Statement warning at foudiv.vhd(51): signal \"rst\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 51 0 0 } }  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "fout~reg0 \\lammy05:cnt2 " "Info: Duplicate register \"fout~reg0\" merged to single register \"\\lammy05:cnt2\"" {  } { { "foudiv.vhd" "" { Text "F:/EDA_Quartus/foudiv/foudiv.vhd" 10 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "78 " "Info: Implemented 78 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "73 " "Info: Implemented 73 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jun 15 22:20:35 2007 " "Info: Processing ended: Fri Jun 15 22:20:35 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}