📄 datasheet.txt
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Datasheet Generated by mig version 1.6 at 星期四 七月 5 14:43:24 2007FPGA : Target Device : xc4vsx35-ff668 Speed grade : -12Options : HDL : vhdl Synthesis tool : foundation_ise Module name : mem_interface_top No of controllers : 1 DCI for data : enabled DCI for address and control: enabled/*******************************************************//* Controller 0 *//*******************************************************/Interface parameters : Frequency : 100 Data width : 16 Depth : 1 ECC : disabledMemory configuration : DDR SDRAM:Components Part number : MT46V16M16P-5BOther Options : DCM : enabled Add test bench : enabled Clocking type : Direct clocking ClockCapableIO(CC) : enabledSelected banks and Pins usage : Data :bank 6(64) -> Number of pins used : 20 bank 10(64) -> Number of pins used : 0 bank 8(64) -> Number of pins used : 0 Address :bank 6(64) -> Number of pins used : 22 bank 10(64) -> Number of pins used : 0 bank 8(64) -> Number of pins used : 0 System control:bank 1(16) -> Number of pins used : 2 bank 2(16) -> Number of pins used : 0 System clock :bank 3(16) -> Number of pins used : 4 bank 4(16) -> Number of pins used : 0 Total IOs used : 48Design parameters : Mode register : Burst Length : 4(010) Burst Type : sequential(0) Cas Latency : 3(011) Operating Mode : normal(00000) Extended mode register : DLL Enable : Enable-Normal(0) Outputdrive Strength: 100%(0)
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