mem_interface_top_idelay_ctrl.vhd

来自「ISE MIG1.6 生成的DDR SDRAM控制器代码（含TESHBENCH）」· VHDL 代码 · 共 50 行

-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  / Vendor: Xilinx
-- \   \   \/ Version: 1.6
--  \   \ Application : MIG
--  /   / Filename: mem_interface_top_idelay_ctrl.vhd
-- /___/   /\ Date Last Modified:  Wed Jun 1 2005
-- \   \  /  \Date Created: Mon May 2 2005
--  \___\/\___\
-- Device: Virtex-4
-- Design Name: DDR1_SDRAM
-- Description: Instantaites the IDELAYCTRL primitive of the Virtex4 device
--		which continously calibrates the IDELAY elements in the region in case of 
--		varying operating conditions. It takes a 200MHz clock as an input.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library UNISIM;
use UNISIM.vcomponents.all;

entity mem_interface_top_idelay_ctrl is
	port( CLK200	: in std_logic;    
	      RESET	: in std_logic;     
	      RDY_STATUS : out std_logic
	    );
end mem_interface_top_idelay_ctrl;

architecture arch of mem_interface_top_idelay_ctrl is

component IDELAYCTRL 
	port( RDY	: out std_logic;
	      REFCLK	: in std_logic;
	      RST	: in std_logic
	     );
end component;

begin

idelayctrl0 : IDELAYCTRL port map 
	    ( RDY	=> RDY_STATUS,
	      REFCLK	=> CLK200,
	      RST	=> RESET
	    );

end arch;