ddr1_test_tb.v

ISE MIG1.6 生成的DDR SDRAM控制器代码（含TESHBENCH）

 //*******************************************************************************
//
//  File name :       top_tb.v
//
//  Description :     This module is the top level for the physical layer. 
// 
//                    
//  Date - revision : 4/18/2005
//
//  Author :          MG
//
//  Contact : e-mail  [e-mail]
//            phone   + 1 800 255 7778 
//
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//              statutory or otherwise, and Xilinx specifically disclaims any 
//              implied warranties of merchantability, non-infringement, or 
//              fitness for a particular purpose. Xilinx does not warrant that 
//              the functions contained in these designs will meet your 
//              requirements, or that the operation of these designs will be 
//              uninterrupted or error free, or that defects in the Designs 
//              will be corrected. Furthermore, Xilinx does not warrant or 
//              make any representations regarding use or the results of the 
//              use of the designs in terms of correctness, accuracy, 
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//
//              LIMITATION OF LIABILITY. In no event will Xilinx or its 
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//              essential purpose of any limited remedies herein. 
//
//  Copyright  2002 Xilinx, Inc.
//  All rights reserved 
// 
//*****************************************************************************

`timescale 1ns / 100ps
`define sg5B
`define X16

module top_tb;

reg        sys_clk_in;
reg        sys_clk_in_L;
reg        sys_rst_in;
reg        clk200_in_L;
reg        clk200_in;

wire [15:0]  ddr_dq;
wire [1:0]   ddr_dqs;
wire [1:0]   ddr_dqs_n;
wire [1:0]   ddr_dm;
wire [0:0]        ddr_clk;
wire [0:0]        ddr_clk_n;
wire [12:0]  ddr_address;
wire [1:0]   ddr_ba;     
wire         ddr_ras_L;  
wire         ddr_cas_L;  
wire         ddr_we_L;   
wire [0:0]    ddr_cs_L;
wire         ddr_cke;
wire         pass;

board_file mem_interface_top0   (
            .SYS_CLK_N(sys_clk_in_L),
            .SYS_CLK_P(sys_clk_in),
            .CLK200_N(clk200_in_L),
            .CLK200_P(clk200_in),
            .SYS_RESET_IN(sys_rst_in),
            .cntrl0_DDR_DQ(ddr_dq),
            .cntrl0_DDR_DQS(ddr_dqs),
            .cntrl0_DDR_DM(ddr_dm),
            .cntrl0_DDR_CK(ddr_clk),
            .cntrl0_DDR_CK_N(ddr_clk_n),
            .cntrl0_DDR_A(ddr_address),
            .cntrl0_DDR_BA(ddr_ba),
            .cntrl0_DDR_RAS_N(ddr_ras_L),
            .cntrl0_DDR_CAS_N(ddr_cas_L),
            .cntrl0_DDR_WE_N(ddr_we_L),
            .cntrl0_DDR_CS_N(ddr_cs_L),
            .cntrl0_DDR_CKE(ddr_cke),
            .cntrl0_ERROR(pass)
            );
           


ddr mt47h16m16ft0 (
                    .Clk(ddr_clk[0]),
                    .Clk_n(ddr_clk_n[0]),
                    .Cke(ddr_cke),
                    .Cs_n(ddr_cs_L[0]),
                    .Ras_n(ddr_ras_L),
                    .Cas_n(ddr_cas_L),
                    .We_n(ddr_we_L),
                    .Dm(ddr_dm[1:0]),
                    .Ba(ddr_ba[1:0]),
                    .Addr(ddr_address),
                    .Dq(ddr_dq[15:0]),
                    .Dqs(ddr_dqs[1:0])
                    );
/*                   
ddr mt47h16m16ft1 (
                    .Clk(ddr_clk[1]),
                    .Clk_n(ddr_clk_n[1]),
                    .Cke(ddr_cke),
                    .Cs_n(ddr_cs_L),
                    .Ras_n(ddr_ras_L),
                    .Cas_n(ddr_cas_L),
                    .We_n(ddr_we_L),
                    .Dm(ddr_dm[3:2]),
                    .Ba(ddr_ba[1:0]),
                    .Addr(ddr_address),
                    .Dq(ddr_dq[31:16]),
                    .Dqs(ddr_dqs[3:2])
                    );
 */

initial
begin
  sys_clk_in   = 1'b0;
  sys_clk_in_L = 1'b1;
  clk200_in_L  = 1'b1;
  clk200_in    = 1'b0;
  sys_rst_in   = 1'b0;
  #60 
  sys_rst_in = 1'b1;
end
  

always
 sys_clk_in = #2.5 ~sys_clk_in; // input clock for memory interface

always
 sys_clk_in_L = #2.5 ~sys_clk_in_L; // input clock for memory interface 

always
 clk200_in = #2.5 ~clk200_in; // 200 MHz input clock for IDELAYCTRL (not to be changed)
 
always
 clk200_in_L = #2.5 ~clk200_in_L; // 200 MHz input clock for IDELAYCTRL (not to be changed)
 
 
endmodule