glbl.v

来自「ISE MIG1.6 生成的DDR SDRAM控制器代码（含TESHBENCH）」· Verilog 代码 · 共 37 行

// $Header: \projects/mig1.x/mig1.5/tool/mig 1.5_b0.21/data/dlib/virtex4/DDR SDRAM/sim/glbl.v,v 1.1 2006/01/02 05:22:11 gnana Exp $

`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

    wire GSR;
    wire GTS;
    wire PRLD;

    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

    assign (weak1, weak0) GSR = GSR_int;
    assign (weak1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule