mem_interface_top.ucf

来自「ISE MIG1.6 生成的DDR SDRAM控制器代码（含TESHBENCH）」· UCF 代码 · 共 132 行

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## 
##  Xilinx, Inc. 2006            www.xilinx.com 
##  星期四 七月 5 14:43:22 2007
##  Generated by mig version 1.6 released on August 1st 2006
##  
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##  File name :       mem_interface_top.ucf
## 
##  Description :     Constraints file
##                    targetted to xc4vsx35-ff668
##
############################################################################ 
############################################################################
# Clock constraints                                                        #
############################################################################

NET "infrastructure0/SYS_CLK_IN" TNM_NET =  "SYS_CLK";
TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 10 ns HIGH 50 %; 


######################################################################################################
# Net Constraints																			  
######################################################################################################


NET "infrastructure0/sys_rst90" TIG; 		
NET "infrastructure0/sys_rst_ref_clk" TIG;
NET "infrastructure0/sys_rst" TIG;
########################################################################

# Controller 0#
# Memory Device DDR SDRAM->Components->MT46V16M16P-5B#
########################################################################


######################################################################################################
# I/O STANDARDS																						 
######################################################################################################

NET  "cntrl0_DDR_DQ[*]"                                     IOSTANDARD = SSTL2_II_DCI;
NET  "cntrl0_DDR_A[*]"                                      IOSTANDARD = SSTL2_II_DCI;
NET  "cntrl0_DDR_BA[*]"                                     IOSTANDARD = SSTL2_II_DCI;
NET  "cntrl0_DDR_CKE"                                       IOSTANDARD = SSTL2_II_DCI;
NET  "cntrl0_DDR_CS_N"                                      IOSTANDARD = SSTL2_II_DCI;
NET  "cntrl0_DDR_RAS_N"                                     IOSTANDARD = SSTL2_II_DCI;
NET  "cntrl0_DDR_CAS_N"                                     IOSTANDARD = SSTL2_II_DCI;
NET  "cntrl0_DDR_WE_N"                                      IOSTANDARD = SSTL2_II_DCI;
NET  "cntrl0_DDR_DM[*]"                                     IOSTANDARD = SSTL2_II_DCI;
NET  "SYS_CLK_P"                                     IOSTANDARD = LVPECL_25;
NET  "SYS_CLK_N"                                     IOSTANDARD = LVPECL_25;
NET  "CLK200_P"                                      IOSTANDARD = LVPECL_25;
NET  "CLK200_N"                                      IOSTANDARD = LVPECL_25;
NET  "SYS_RESET_IN"                                  IOSTANDARD = LVCMOS25;
NET  "cntrl0_DDR_DQS[*]"                                    IOSTANDARD = SSTL2_II_DCI;
NET  "cntrl0_DDR_CK[*]"                                     IOSTANDARD = DIFF_SSTL2_II_DCI;
NET  "cntrl0_DDR_CK_N[*]"                                   IOSTANDARD = DIFF_SSTL2_II_DCI;

######################################################################################################
# Area Group Constraints																			  
######################################################################################################





INST "top_00/iobs_00/data_path_iobs_00/v4_dqs_iob0*" AREA_GROUP=dqs_gp0;
AREA_GROUP "dqs_gp0" COMPRESSION = 0;  # no compression 

INST "top_00/iobs_00/data_path_iobs_00/v4_dqs_iob1*" AREA_GROUP=dqs_gp1;
AREA_GROUP "dqs_gp1" COMPRESSION = 0;  # no compression 



INST "top_00/data_path_00/tap_logic_00/data_tap_inc_0*" AREA_GROUP=data_tap_gp0;
AREA_GROUP "data_tap_gp0" COMPRESSION = 0;  # no compression







NET  "cntrl0_DDR_DQ[0]"                                      LOC = "D10" ;	      #Bank 6
NET  "cntrl0_DDR_DQ[1]"                                      LOC = "C10" ;	      #Bank 6
NET  "cntrl0_DDR_DQ[2]"                                      LOC = "D9" ;	      #Bank 6
NET  "cntrl0_DDR_DQ[3]"                                      LOC = "C8" ;	      #Bank 6
NET  "cntrl0_DDR_DQ[4]"                                      LOC = "A8" ;	      #Bank 6
NET  "cntrl0_DDR_DQ[5]"                                      LOC = "A7" ;	      #Bank 6
NET  "cntrl0_DDR_DQ[6]"                                      LOC = "D8" ;	      #Bank 6
NET  "cntrl0_DDR_DQ[7]"                                      LOC = "F10" ;	      #Bank 6
NET  "cntrl0_DDR_DQ[8]"                                      LOC = "A6" ;	      #Bank 6
NET  "cntrl0_DDR_DQ[9]"                                      LOC = "A5" ;	      #Bank 6
NET  "cntrl0_DDR_DQ[10]"                                     LOC = "E9" ;	      #Bank 6
NET  "cntrl0_DDR_DQ[11]"                                     LOC = "F9" ;	      #Bank 6
NET  "cntrl0_DDR_DQ[12]"                                     LOC = "F8" ;	      #Bank 6
NET  "cntrl0_DDR_DQ[13]"                                     LOC = "G8" ;	      #Bank 6
NET  "cntrl0_DDR_DQ[14]"                                     LOC = "B7" ;	      #Bank 6
NET  "cntrl0_DDR_DQ[15]"                                     LOC = "C7" ;	      #Bank 6
NET  "cntrl0_DDR_A[12]"                                      LOC = "C6" ;	      #Bank 6
NET  "cntrl0_DDR_A[11]"                                      LOC = "G9" ;	      #Bank 6
NET  "cntrl0_DDR_A[10]"                                      LOC = "A3" ;	      #Bank 6
NET  "cntrl0_DDR_A[9]"                                       LOC = "B3" ;	      #Bank 6
NET  "cntrl0_DDR_A[8]"                                       LOC = "A4" ;	      #Bank 6
NET  "cntrl0_DDR_A[7]"                                       LOC = "B4" ;	      #Bank 6
NET  "cntrl0_DDR_A[6]"                                       LOC = "C4" ;	      #Bank 6
NET  "cntrl0_DDR_A[5]"                                       LOC = "D4" ;	      #Bank 6
NET  "cntrl0_DDR_A[4]"                                       LOC = "E7" ;	      #Bank 6
NET  "cntrl0_DDR_A[3]"                                       LOC = "D6" ;	      #Bank 6
NET  "cntrl0_DDR_A[2]"                                       LOC = "E6" ;	      #Bank 6
NET  "cntrl0_DDR_A[1]"                                       LOC = "E5" ;	      #Bank 6
NET  "cntrl0_DDR_A[0]"                                       LOC = "F7" ;	      #Bank 6
NET  "cntrl0_DDR_BA[1]"                                      LOC = "G7" ;	      #Bank 6
NET  "cntrl0_DDR_BA[0]"                                      LOC = "C2" ;	      #Bank 6
NET  "cntrl0_DDR_CKE"                                        LOC = "H8" ;	      #Bank 6
NET  "cntrl0_DDR_CS_N"                                       LOC = "H7" ;	      #Bank 6
NET  "cntrl0_DDR_RAS_N"                                      LOC = "D3" ;	      #Bank 6
NET  "cntrl0_DDR_CAS_N"                                      LOC = "E4" ;	      #Bank 6
NET  "cntrl0_DDR_WE_N"                                       LOC = "E3" ;	      #Bank 6
NET  "cntrl0_DDR_DM[0]"                                      LOC = "E10" ;	      #Bank 6
NET  "cntrl0_DDR_DM[1]"                                      LOC = "C5" ;	      #Bank 6
NET  "SYS_CLK_P"                                      LOC = "B15" ;	      #Bank 3
NET  "SYS_CLK_N"                                      LOC = "B14" ;	      #Bank 3
NET  "CLK200_P"                                       LOC = "C15" ;	      #Bank 3
NET  "CLK200_N"                                       LOC = "C14" ;	      #Bank 3
NET  "SYS_RESET_IN"                                   LOC = "F14" ;	      #Bank 1
NET  "cntrl0_DDR_DQS[0]"                                     LOC = "B6" ;	      #Bank 6
NET  "cntrl0_DDR_DQS[1]"                                     LOC = "G10" ;	      #Bank 6
NET  "cntrl0_DDR_CK[0]"                                      LOC = "A9" ;	      #Bank 6
NET  "cntrl0_DDR_CK_N[0]"                                    LOC = "B9" ;	      #Bank 6