mem_interface_top.prj

ISE MIG1.6 生成的DDR SDRAM控制器代码（含TESHBENCH）

vhdl  work  ../rtl/mem_interface_top.vhd
vhdl  work  ../rtl/mem_interface_top_backend_fifos_0.vhd
vhdl  work  ../rtl/mem_interface_top_controller_iobs_0.vhd
vhdl  work  ../rtl/mem_interface_top_data_path_0.vhd
vhdl  work  ../rtl/mem_interface_top_data_path_iobs_0.vhd
vhdl  work  ../rtl/mem_interface_top_data_tap_inc.vhd
vhdl  work  ../rtl/mem_interface_top_data_write_0.vhd
vhdl  work  ../rtl/mem_interface_top_ddr_controller_0.vhd
vhdl  work  ../rtl/mem_interface_top_idelay_ctrl.vhd
vhdl  work  ../rtl/mem_interface_top_infrastructure.vhd
vhdl  work  ../rtl/mem_interface_top_infrastructure_iobs_0.vhd
vhdl  work  ../rtl/mem_interface_top_iobs_0.vhd
vhdl  work  ../rtl/mem_interface_top_parameters_0.vhd
vhdl  work  ../rtl/mem_interface_top_pattern_compare8.vhd
vhdl  work  ../rtl/mem_interface_top_RAM_D_0.vhd
vhdl  work  ../rtl/mem_interface_top_rd_data_0.vhd
vhdl  work  ../rtl/mem_interface_top_rd_data_fifo_0.vhd
vhdl  work  ../rtl/mem_interface_top_rd_wr_addr_fifo_0.vhd
vhdl  work  ../rtl/mem_interface_top_tap_ctrl_0.vhd
vhdl  work  ../rtl/mem_interface_top_tap_logic_0.vhd
vhdl  work  ../rtl/mem_interface_top_top_0.vhd
vhdl  work  ../rtl/mem_interface_top_user_interface_0.vhd
vhdl  work  ../rtl/mem_interface_top_v4_dm_iob.vhd
vhdl  work  ../rtl/mem_interface_top_v4_dq_iob.vhd
vhdl  work  ../rtl/mem_interface_top_v4_dqs_iob.vhd
vhdl  work  ../rtl/mem_interface_top_wr_data_fifo_16.vhd