mig.prj

ISE MIG1.6 生成的DDR SDRAM控制器代码（含TESHBENCH）

<?xml version="1.0" encoding="UTF-8"?>
<Project controllerNumber="0" NoOfControllers="1" MemoryType="DDR SDRAM/Components/MT46V16M16P-5B" >
    <SelectedPins></SelectedPins>
    <ReservedPins></ReservedPins>
    <DCM>1</DCM>
    <ModuleName>mem_interface_top</ModuleName>
    <dci_data>1</dci_data>
    <dci_address>1</dci_address>
    <FPGADevice/>
    <Controller number="0" >
        <MemoryDevice>DDR SDRAM/Components/MT46V16M16P-5B</MemoryDevice>
        <Clocking>Direct clocking</Clocking>
        <CCCheck>1</CCCheck>
        <Frequency>100</Frequency>
        <DataWidth>16</DataWidth>
        <DeepMemory>1</DeepMemory>
        <ECC>0</ECC>
        <WritePipeLine>4</WritePipeLine>
        <BankSelection>
            <Bank Control="0" Address="1" SysClk="0" Dwrite="0" Data="1" name="6" wasso="64" />
            <Bank Control="0" Address="1" SysClk="0" Dwrite="0" Data="1" name="10" wasso="64" />
            <Bank Control="0" Address="1" SysClk="0" Dwrite="0" Data="1" name="8" wasso="64" />
            <Bank Control="0" Address="0" SysClk="1" Dwrite="0" Data="0" name="3" wasso="16" />
            <Bank Control="1" Address="0" SysClk="0" Dwrite="0" Data="0" name="1" wasso="16" />
            <Bank Control="1" Address="0" SysClk="0" Dwrite="0" Data="0" name="2" wasso="16" />
            <Bank Control="0" Address="0" SysClk="1" Dwrite="0" Data="0" name="4" wasso="16" />
        </BankSelection>
        <mrBurstLength name="Burst Length" >4(010)</mrBurstLength>
        <mrBurstType name="Burst Type" >sequential(0)</mrBurstType>
        <mrCasLatency name="Cas Latency" >3(011)</mrCasLatency>
        <mrMode name="Operating Mode" >normal(00000)</mrMode>
        <emrDllEnable name="DLL Enable" >Enable-Normal(0)</emrDllEnable>
        <emrOutputDriveStrength name="Outputdrive Strength" >100%(0)</emrOutputDriveStrength>
    </Controller>
</Project>