mem_interface_top_v4_dm_iob.vhd

ISE MIG1.6 生成的DDR SDRAM控制器代码（含TESHBENCH）

-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  / Vendor: Xilinx
-- \   \   \/ Version: 1.6
--  \   \ Application : MIG
--  /   / Filename: mem_interface_top_v4_dm_iob.vhd
-- /___/   /\ Date Last Modified:  Wed Jun 1 2005
-- \   \  /  \Date Created: Mon May 2 2005
--  \___\/\___\
-- Device: Virtex-4
-- Design Name: DDR1_SDRAM
-- Description: Places the data mask signals into the IOBs.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library UNISIM;
use UNISIM.vcomponents.all;

entity mem_interface_top_v4_dm_iob is
	port( CLK90            : in std_logic;
	      MASK_DATA_RISE   : in std_logic;
	      MASK_DATA_FALL   : in std_logic;
	      DDR_DM           : out std_logic
	    );
end mem_interface_top_v4_dm_iob;

architecture arch of mem_interface_top_v4_dm_iob is

component ODDR
	generic( SRTYPE		: string := "SYNC";
		 DDR_CLK_EDGE	: string := "SAME_EDGE"
	       );
	port( Q		: out std_logic;
	      C		: in std_logic;
	      CE	: in std_logic;
	      D1	: in std_logic;
	      D2	: in std_logic;
	      R		: in std_logic;
	      S		: in std_logic
	    );
end component;

signal vcc : std_logic;
signal gnd : std_logic;




begin

vcc <= '1';
gnd <= '0';

oddr_dm: ODDR
--	generic map( SRTYPE	=> "SYNC",
--		 DDR_CLK_EDGE	=> "SAME_EDGE"
--	       );
	port map( Q		=> DDR_DM,
		  C		=> CLK90,
		  CE		=> vcc,
		  D1		=> MASK_DATA_RISE,
		  D2		=> MASK_DATA_FALL,
		  R		=> gnd,
		  S		=> gnd
		);		

end arch;