mem_interface_top_tap_ctrl_0.vhd

ISE MIG1.6 生成的DDR SDRAM控制器代码（含TESHBENCH）

  elsif(dly_inc = '1' and first_edge = '1' and first_edge_cnt /= "000") then---changed from first_edge_cnt != 3'b001 to first_edge_cnt != 3'b000 so that assignment of rising_edge only happens when first_edge_cnt == 001//////////////////////////////////      
       first_edge_cnt	      <= first_edge_cnt - '1';
  end if;
 end if;
end process;
   
process(CLK)
begin 
 if(CLK'event and CLK = '1') then     
  if (reset_int = '1') then
       second_edge_tap_count  <= "000000";
  elsif ((transition = "10") and (second_edge = '0')) then
       second_edge_tap_count  <= tap_counter;
  end if;
 end if;
end process;

       
process(CLK)
begin 
 if(CLK'event and CLK = '1') then     
  if (reset_int = '1') then
       pulse_width_tap_count <= "000000";
  elsif (second_edge_r1 = '1') then
       pulse_width_tap_count <= (second_edge_tap_count - first_edge_tap_count);
  end if;
 end if;
end process;

   
process(CLK)
begin 
 if(CLK'event and CLK = '1') then     
  if (reset_int = '1') then
       pulse_center_tap_count <= "000000";
  elsif (second_edge_r2 = '1') then
       pulse_center_tap_count <= '0' & pulse_width_tap_count(5 downto 1);  -- Shift right to divide by 2 and find pulse center
  end if;
 end if;
end process;

       
process(CLK)
begin 
 if(CLK'event and CLK = '1') then     
  if (reset_int = '1') then
       data_bit_tap_count     <= "000000";
  elsif (second_edge_r3 = '1') then -- 2 edges detected
       data_bit_tap_count  <= first_edge_tap_count + pulse_center_tap_count; --+ "000100";
  elsif ((transition = "01") and ((tap_counter = "111111"))) then -- Only 1 edge detected
	if (first_edge_tap_count(5) = '0') then
		data_bit_tap_count  <= first_edge_tap_count + "010000";
	else
		data_bit_tap_count  <= first_edge_tap_count - "010000";
	end if;
  elsif ((transition = "00") and ((tap_counter = "111111"))) then -- No edges detected
       data_bit_tap_count  <= "100000";
  end if;
 end if;
end process;


-- Logic required to determine whether the registered DQS is on the edge of meeting setup time in the FPGA clock domain. 
-- If DQS is on the edge, then the vector 'flag' will not be "1111" or "0000" and edge detection will not be executed.
-- If DQS is not on the edge, then the vector 'flag' will be "1111" or "0000" and edge detection will be executed.
   
process(CLK)
begin 
  if CLK'event and CLK = '1' then 
    if (reset_int = '1') then
         flag <= ( others => '0');
    elsif (detect_edge_idle_r3 = '1' or idelay_inc_idle_r3 = '1' or idelay_rst_idle_r3 = '1') then
         if (curr_dqs_level /= prev_dqs_level) then
           flag(0) <= '0';
         else
           flag(0) <= '1';
         end if;
   elsif (detect_edge_idle_r4 = '1' or idelay_inc_idle_r4 = '1' or  idelay_rst_idle_r4 = '1') then
         if (curr_dqs_level /= prev_dqs_level) then
           flag(1) <= '0';
         else
           flag(1) <= '1';
         end if;
   elsif (detect_edge_idle_r5 = '1' or idelay_inc_idle_r5 = '1' or idelay_rst_idle_r5 = '1') then
         if (curr_dqs_level /= prev_dqs_level) then
           flag(2) <= '0';
         else
           flag(2) <= '1';
         end if;
   elsif (detect_edge_idle_r6 = '1' or idelay_inc_idle_r6 = '1' or idelay_rst_idle_r6 = '1') then
         if (curr_dqs_level /= prev_dqs_level) then
           flag(3) <= '0';
         else
           flag(3) <= '1';
         end if;
 
   end if;
 end if;
end process; 


-- First and second edge assignment logic 
process(CLK)
begin
 if(CLK'event and CLK = '1') then     
  if (reset_int = '1') then         
	 transition(1 downto 0) <= "00";
    rising            <= '0';
  elsif ((dly_after_first_cnt = "0000") and (state = detect_edge) and ((flag = X"0") or (flag = X"F"))) then
       if ((curr_dqs_level /= prev_dqs_level) and (transition_rst = '0') and (tap_counter > "000000")) then
         transition <= transition + '1';
         if ((curr_dqs_level = '0') and (prev_dqs_level = '1')) then
               rising <= '1';
         else
               rising <= '0';
         end if;
     end if;
  elsif (transition_rst = '1') then
       transition <= "00";
  else
       transition <= transition;
  end if;
 end if;
end process;
   
   
process(CLK)
begin
 if(CLK'event and CLK = '1') then     
  if (reset_int = '1') then         
	 transition_rst  <= '0';
         first_edge      <= '0';
         second_edge     <= '0';
  else
   case transition is
         when "01" =>
                  first_edge <= '1';

	 when "10" =>
                  if (transition_rst = '1') then
                      second_edge <= '0';
                      transition_rst <= '0';
                  else
                      second_edge    <= '1';
                      transition_rst <= '1';
                  end if;
         when others =>
                    first_edge     <= '0'; 
                    second_edge    <= '0';
   end case;
  end if;
 end if;
end process;
     
-- State Machine for edge detection and midpoint determination   
process(CLK)
begin
 if(CLK'event and CLK = '1') then     
  if (reset_int = '1') then   -- DQS IDELAY in reset
         dly_rst           <= '1';
         dly_ce            <= '0';
         dly_inc           <= '0';
         idelay_rst_idle   <= '0';
         detect_edge_idle  <= '0';
         idelay_inc_idle   <= '0';
         prev_dqs_level    <= curr_dqs_level;
         state(2 downto 0)        <= idelay_rst;
  elsif ((CTRL_DUMMYREAD_START = '1') and (sel_complete = '0')) then
     case state is
         when "000" =>  -- idelay_rst 
                   dly_rst         <= '1';
                   dly_ce          <= '0';
                   dly_inc         <= '0';
                   idelay_rst_idle <= '1';
                   state(2 downto 0)      <= idle;
         when "001" =>  -- idle
                     dly_rst          <= '0';
                     dly_ce           <= '0';
                     dly_inc          <= '0';
                     idelay_rst_idle  <= '0';
                     detect_edge_idle <= '0';
                     idelay_inc_idle  <= '0';
                   if (idelay_rst_idle_r5 = '1') then
                     state(2 downto 0) <= idelay_inc;
                   elsif ((idelay_inc_idle_r6 = '1') or ((detect_edge_idle_r6 = '1') and (second_edge_r2 = '0') and (tap_counter /= "111111"))) then
                     state(2 downto 0) <= detect_edge;
                   else 
                     state(2 downto 0) <= idle;
                   end if;
         when "010" =>  -- idelay_inc 
                   dly_rst         <= '0';
                   dly_ce          <= '1';
                   dly_inc         <= '1';
                   idelay_inc_idle <= '1';
                   state(2 downto 0)      <= idle;
                   if((flag(3 downto 0) = X"0") or (flag(3 downto 0) = X"F")) then
                    prev_dqs_level  <= curr_dqs_level;
                   else 
		    prev_dqs_level   <= prev_dqs_level;
                   end if;   

	 when "011" =>  -- detect_edge 
                   dly_rst          <= '0';
                   dly_ce           <= '1';
                   dly_inc          <= '1';
                   detect_edge_idle <= '1';
                   state(2 downto 0)       <= idle;
                   if((flag(3 downto 0) = X"0") or (flag(3 downto 0) = X"F")) then
                    prev_dqs_level  <= curr_dqs_level;
                   else 
		    prev_dqs_level   <= prev_dqs_level;
                   end if;       
         when others =>
                    dly_rst          <= '0';          
                    dly_ce           <= '0';          
                    dly_inc          <= '0';
                    idelay_rst_idle  <= '0';
                    detect_edge_idle <= '0';
                    idelay_inc_idle  <= '0';          
                    prev_dqs_level   <= curr_dqs_level;
                    state(2 downto 0)       <= idle;   
     end case;
   else
         dly_rst          <= '0';
         dly_ce           <= '0';
         dly_inc          <= '0';
         idelay_rst_idle  <= '0';
         detect_edge_idle <= '0';
         idelay_inc_idle  <= '0';
         prev_dqs_level   <= curr_dqs_level;
         state		  <= idelay_rst;
  end if;
 end if;
end process;
   
end arch;