mem_interface_top_infrastructure.vhd

ISE MIG1.6 生成的DDR SDRAM控制器代码（含TESHBENCH）

-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  / Vendor: Xilinx
-- \   \   \/ Version: 1.6
--  \   \ Application : MIG
--  /   / Filename: mem_interface_top_infrastructure.vhd
-- /___/   /\ Date Last Modified:  Wed Jun 1 2005
-- \   \  /  \Date Created: Mon May 2 2005
--  \___\/\___\
-- Device: Virtex-4
-- Design Name: DDR1_SDRAM
-- Description: Instantiates the DCM of the FPGA device. The system clock is given 
--		as the input and two clocks that are phase shifted by 90 degrees are taken out.
--		It also give the reset signals in phase with the clocks.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library UNISIM;
use UNISIM.vcomponents.all;

entity mem_interface_top_infrastructure is
	port
	(
	 
	  
	      SYS_CLK_N			: in std_logic; 
		  SYS_CLK_P        	: in std_logic; 
		  CLK200_N         	: in std_logic; 
		  CLK200_P          : in std_logic;



 	  
	      SYS_RESET_IN     	: in std_logic;

	      
	      CLK               : out std_logic;
	      CLK90            	: out std_logic;
	      CLK200           	: out std_logic;
	      CLK50             : out std_logic;
	      REFRESH_CLK      	: out std_logic; 



	      sys_rst          	: out std_logic;
	      sys_rst90         : out std_logic;
	      sys_rst_ref_clk_1 : out std_logic
	    );
end mem_interface_top_infrastructure;

architecture arch of mem_interface_top_infrastructure is



component IBUFGDS_LVPECL_25
	port( I  : in std_logic;
	      IB : in std_logic;
	      O  : out std_logic
	    );
end component;

component DCM_BASE
	generic(
		  CLKDV_DIVIDE : real := 16.0;
		  CLKFX_DIVIDE : integer := 8;
		  CLKFX_MULTIPLY : integer := 2;                                
		  DCM_PERFORMANCE_MODE : string := "MAX_SPEED";
		  DFS_FREQUENCY_MODE : string := "LOW";                
		  DLL_FREQUENCY_MODE : string := "LOW";
		  DUTY_CYCLE_CORRECTION : boolean := TRUE;
		  FACTORY_JF : bit_vector := X"F0F0"
	       );
port(
		CLK0	: out std_logic;
	      CLK180	: out std_logic;
	      CLK270	: out std_logic;	
	      CLK2X	: out std_logic;
	      CLK2X180	: out std_logic;
	      CLK90	: out std_logic;
	      CLKDV	: out std_logic;
	      CLKFX	: out std_logic;
	      CLKFX180	: out std_logic;
	      LOCKED	: out std_logic;
	      CLKFB	: in std_logic;
	      CLKIN	: in std_logic;
	      RST	: in std_logic
	    );
end component;

component BUFG
	port( O	: out std_logic;
	      I : in std_logic
	    );
end component;







signal clk0_bufg_in		: std_logic;   
signal clk90_bufg_in 	: std_logic; 
signal clkdv_bufg_in 	: std_logic; 
signal clk50_bufg_in 	: std_logic; 
signal clk0_bufg_out 	: std_logic; 
signal clk90_bufg_out	: std_logic; 
signal clkdv_bufg_out	: std_logic; 
signal clk0_bufg1_out	: std_logic; 
signal clk50_bufg_out	: std_logic; 
signal SYS_CLK_IN   	: std_logic; 
signal LOCKED			: std_logic;



signal sys_rst_0        : std_logic;  
signal sys_rst_1        : std_logic;  
signal sys_rst_2        : std_logic;  
signal sys_rst_3        : std_logic;  
signal sys_rst90_0      : std_logic;  
signal sys_rst90_1      : std_logic;  
signal sys_rst90_2      : std_logic;  
signal sys_rst90_3      : std_logic;  
signal sys_rst_ref_clk_0: std_logic;  
signal sys_rst_ref_clk_2: std_logic;  
signal sys_rst_ref_clk  : std_logic;  
signal REF_CLK200_IN	: std_logic; 
signal SYS_RESET    	: std_logic; 
signal clk_int          : std_logic;
signal clk90_int        : std_logic;
signal clk50_int        : std_logic;



begin



CLK         <= clk0_bufg_out;  
CLK90       <= clk90_bufg_out; 
clk_int     <= clk0_bufg_out;  
clk90_int   <= clk90_bufg_out; 
CLK200      <= clk0_bufg1_out; 
REFRESH_CLK <= clkdv_bufg_out; 
CLK50       <= clk50_bufg_out; 
clk50_int   <= clk50_bufg_out; 
SYS_RESET   <= not SYS_RESET_IN;








lvds_sys_clk_input: IBUFGDS_LVPECL_25 port map
	    ( I  => SYS_CLK_P,
	      IB => SYS_CLK_N,
	      O  => SYS_CLK_IN
	    );

lvpecl_clk200_in: IBUFGDS_LVPECL_25 port map
	    ( I  => CLK200_P,
	      IB => CLK200_N,
	      O  => REF_CLK200_IN 
	    );

DCM_BASE0: DCM_BASE 
	generic map( DLL_FREQUENCY_MODE    => "LOW",
		     DUTY_CYCLE_CORRECTION => TRUE,
		     CLKDV_DIVIDE	   => 16.0,
		     CLKFX_MULTIPLY	   => 2,
		     CLKFX_DIVIDE	   => 8
		   )
	port map( CLK0		=> clk0_bufg_in,
		  CLK180	=> open,
		  CLK270	=> open,
		  CLK2X		=> open,
		  CLK2X180	=> open,
		  CLK90		=> clk90_bufg_in,
		  CLKDV		=> clkdv_bufg_in,
		  CLKFX		=> clk50_bufg_in,
		  CLKFX180	=> open,
		  LOCKED	=> LOCKED,
		  CLKFB		=> clk0_bufg_out,
		  CLKIN		=> SYS_CLK_IN,
		  RST		=> SYS_RESET
		);

dcm_clk0: BUFG port map
	( O	=> clk0_bufg_out,	
	  I	=> clk0_bufg_in
	);

dcm_clk90: BUFG port map
	( O	=> clk90_bufg_out,	
	  I	=> clk90_bufg_in
	);

dcm_clkdv: BUFG port map
	( O	=> clkdv_bufg_out,	
	  I	=> clkdv_bufg_in
	);

dcm_clkfx: BUFG port map
	( O	=> clk50_bufg_out,	
	  I	=> clk50_bufg_in
	);

dcm1_clk0: BUFG port map
	( O	=> clk0_bufg1_out,	
	  I	=> REF_CLK200_IN
	);

process(clk_int)
begin
 if(clk_int'event and clk_int = '1') then
  if((SYS_RESET = '1') or 
(LOCKED = '0')
  or (sys_rst_ref_clk = '1')) then
	sys_rst_0 <= '1';
	sys_rst_1 <= '1';
	sys_rst_2 <= '1';
	sys_rst_3 <= '1';
	sys_rst   <= '1';
  else
	sys_rst_0 <= '0';
	sys_rst_1 <= sys_rst_0;
	sys_rst_2 <= sys_rst_1;
	sys_rst_3 <= sys_rst_2;
	sys_rst   <= sys_rst_3;
  end if;
 end if;
end process;

process(clk90_int)
begin
 if(clk90_int'event and clk90_int = '1') then
  if((SYS_RESET = '1') or 
(LOCKED = '0')
  or (sys_rst_ref_clk = '1')) then
      sys_rst90_0 <= '1';
      sys_rst90_1 <= '1';
      sys_rst90_2 <= '1';
      sys_rst90_3 <= '1';
      sys_rst90   <= '1';
  else
      sys_rst90_0 <= '0';
      sys_rst90_1 <= sys_rst90_0;
      sys_rst90_2 <= sys_rst90_1;
      sys_rst90_3 <= sys_rst90_2;
      sys_rst90   <= sys_rst90_3;
  end if;
 end if;
end process;

process(clk50_int)
begin
 if(clk50_int'event and clk50_int = '1') then
  if ((SYS_RESET = '1') or 
(LOCKED = '0')
 ) then
      sys_rst_ref_clk_0 <= '1';
      sys_rst_ref_clk_1 <= '1';
      sys_rst_ref_clk_2 <= '1';
      sys_rst_ref_clk   <= '1';
  else
      sys_rst_ref_clk_0 <= '0';
      sys_rst_ref_clk_1 <= sys_rst_ref_clk_0;
      sys_rst_ref_clk_2 <= sys_rst_ref_clk_0;
      sys_rst_ref_clk   <= sys_rst_ref_clk_2;
  end if;
 end if;
end process;


end arch;