buffer.vhd.bak

来自「FIFO的Verilog程序 已在modelsim中编译通过 并且可以通过DC进」· BAK 代码 · 共 25 行

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;

ENTITY Buffer IS
    PORT(
        wclk   :   IN   std_logic;
        rstb   :   IN   std_logic;
        
        ISOP   :   IN   std_logic;
        IEOP   :   IN   std_logic;
        IVALID :   IN   std_logic;
        IREADY :   IN   std_logic;
        IDATA  :   IN   std_logic_vector(7 DOWNTO 0);

        wclk   :   IN   std_logic;
        
        OSOP   :   IN   std_logic;
        OEOP   :   IN   std_logic;
        OVALID :   IN   std_logic;
        ODATA  :   IN   std_logic_vector(7 DOWNTO 0)
        );
END writer_pointer;

ARCHITECTURE behav OF writer_pointer IS