taix_fee.tan.summary

verilog HDL编写的出租车计费系统

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.800 ns
From           : j
To             : qdd:qdd1|b
From Clock     : --
To Clock       : a
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 14.600 ns
From           : led_show:led|led_sel[7]
To             : e[7]
From Clock     : a
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -4.800 ns
From           : p
To             : qdd:qdd1|c
From Clock     : --
To Clock       : a
Failed Paths   : 0

Type           : Clock Setup: 'a'
Slack          : N/A
Required Time  : None
Actual Time    : 75.19 MHz ( period = 13.300 ns )
From           : km_counter:km_c|n[0]
To             : km_counter:km_c|n[31]
From Clock     : a
To Clock       : a
Failed Paths   : 0

Type           : Clock Hold: 'a'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : qdd:qdd1|b
To             : qdd:qdd1|k2o
From Clock     : a
To Clock       : a
Failed Paths   : 3

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 3

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