write_synchronizer.v

来自「同步及异步时序电路fifo源程序及其测试程序.rar - fifo源程序」· Verilog 代码 · 共 17 行

module write_synchronizer(write_synch,write_to_FIFO,clock,reset);
    output  write_synch;
    input   write_to_FIFO;
    input   clock,reset;
    reg     meta_synch,write_synch;
    
    always @(negedge clock)
     if(reset==1)begin
         meta_synch<=0;
         write_synch<=0;
     end
     else begin
         meta_synch<=write_to_FIFO;
         write_synch<=write_synch?0:meta_synch;
     end
endmodule