_primary.vhd

来自「同步及异步时序电路fifo源程序及其测试程序.rar - fifo源程序」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity write_synchronizer is
    port(
        write_synch     : out    vl_logic;
        write_to_FIFO   : in     vl_logic;
        clock           : in     vl_logic;
        reset           : in     vl_logic
    );
end write_synchronizer;