_primary.vhd

来自「同步及异步时序电路fifo源程序及其测试程序.rar - fifo源程序」· VHDL 代码 · 共 26 行

library verilog;
use verilog.vl_types.all;
entity FIFO_Buffer is
    generic(
        stack_width     : integer := 32;
        stack_height    : integer := 8;
        stack_ptr_width : integer := 3;
        AE_level        : integer := 2;
        AF_level        : integer := 6;
        HF_level        : integer := 4
    );
    port(
        Data_out        : out    vl_logic_vector;
        stack_full      : out    vl_logic;
        stack_almost_full: out    vl_logic;
        stack_half_full : out    vl_logic;
        stack_almost_empty: out    vl_logic;
        stack_empty     : out    vl_logic;
        Data_in         : in     vl_logic_vector;
        write_to_stack  : in     vl_logic;
        read_from_stack : in     vl_logic;
        clk             : in     vl_logic;
        rst             : in     vl_logic
    );
end FIFO_Buffer;