transcript

MODELSIM开发的模拟CPU

# Reading C:/Modeltech_6.0/tcl/vsim/pref.tcl 
# //  ModelSim SE 6.0 Aug 19 2004 
# //
# //  Copyright Mentor Graphics Corporation 2004
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
#  OpenFile "C:/CPUNEW/CPUNEW2.mpf" 
# Loading project CPUNEW2
# Compile of cpu.vhd was successful.
# Compile of raw.vhd was successful.
# Compile of top.vhd failed with 1 errors.
# 3 compiles, 1 failed with 1 error. 
# Compile of cpu.vhd was successful.
# Compile of raw.vhd was successful.
# Compile of top.vhd failed with 1 errors.
# 3 compiles, 1 failed with 1 error. 
# Compile of cpu.vhd was successful.
# Compile of raw.vhd was successful.
# Compile of top.vhd failed with 1 errors.
# 3 compiles, 1 failed with 1 error. 
# Compile of top.vhd failed with 1 errors.
# Compile of top.vhd failed with 1 errors.
# Compile of cpu.vhd was successful.
# Compile of raw.vhd was successful.
# Compile of top.vhd was successful.
# 3 compiles, 0 failed with no errors. 
vsim work.top
# vsim work.top 
# Loading C:\Modeltech_6.0\win32/../std.standard
# Loading C:\Modeltech_6.0\win32/../ieee.std_logic_1164(body)
# Loading C:\Modeltech_6.0\win32/../ieee.std_logic_arith(body)
# Loading work.commonconstants
# Loading work.top(toparch)
# Loading work.ram(ramarch)
# Loading C:\Modeltech_6.0\win32/../ieee.std_logic_unsigned(body)
# Loading work.cpu(cpuarch)
view wave
# .wave
do C:/CPUNEW/stimulus.do