raw.vhd

来自「MODELSIM开发的模拟CPU」· VHDL 代码 · 共 41 行

package commonConstants is
	constant wordSize: integer := 32;
	constant adrLength: integer := 32;
end package commonConstants;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.commonConstants.all;

entity ram is port (
        reset, en, r_w: in STD_LOGIC;
        aBus: in STD_LOGIC_VECTOR(adrLength-1 downto 0);
        dBus: inout STD_LOGIC_VECTOR(wordSize-1 downto 0));
end ram;

architecture ramArch of ram is
constant resAdrLength: integer := 6; -- address length restricted within architecture
constant memSize: integer := 2**resAdrLength;
type ram_typ is array(0 to memSize-1) of STD_LOGIC_VECTOR(wordSize-1 downto 0);
signal ram: ram_typ;
begin
	process(reset, en, r_w, aBus, dBus) begin
	  	if reset = '1' then
		      	-- basic instruction check
	        	  ram(0)  <= x"10000001"; -- immediate load
		
		        ram(1) <= x"a0000000"; -- add
		        ram(2) <= x"40000003"; -- brZero
		      
		        ram(4) <= x"00000000"; -- halt

		elsif en = '1' and r_w = '0' then
	  		ram(conv_integer(unsigned(aBus(resAdrLength-1 downto 0)))) <= dBus;
		end if;
	end process;
	dBus <= ram(conv_integer(unsigned(aBus(resAdrLength-1 downto 0))))
  			when reset = '0' and en = '1' and r_w = '1' else
			(dbus'range => 'Z');
end ramArch;